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| EM78P510N 8-Bit Microprocessor with OTP ROM Product Specification Doc. Version 0.9 ELAN MICROELECTRONICS CORP. September 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation Copyright (c) 2006 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (USA) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220 Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 2 3 4 5 5 6 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Application................................................................................................................. 3 Pin Assignment ......................................................................................................... 3 Pin Description.......................................................................................................... 7 Functional Block Diagram.......................................................................................11 Function Description .............................................................................................. 12 6.1 6.2 Register Configuration...................................................................................... 12 6.1.1 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12 6.2.13 6.2.14 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19 6.2.20 6.2.21 6.2.22 6.2.23 6.2.24 6.2.25 6.2.26 6.2.27 6.2.28 6.2.29 6.2.30 R PAGE Register Configuration ........................................................................12 R0 (Indirect Addressing Register) .....................................................................12 R1 (TCC) ...........................................................................................................12 R2 (Program Counter).......................................................................................12 R3 (Status, Page Selection) ..............................................................................13 R4 (RAM Select Register).................................................................................14 Bank 0 R5 (RAM Bank Select Register) ...........................................................15 Bank 0 R6 (Program Page Select Register) .....................................................15 Bank 0 R7 (Port 7).............................................................................................15 Bank 0 R8 (Port 8).............................................................................................15 Bank 0 R9 (Port 9).............................................................................................16 Bank 0 RA (Port A) ............................................................................................16 Bank 0 RB (Port B)............................................................................................16 Bank 0 RC SCCR (System Clock Control Register) .........................................16 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)...........................17 Bank 0 RE IMR (Interrupt Mask Register).........................................................18 Bank 0 RF ISR (Interrupt Status Register) ........................................................18 Bank 1 R5 LCDCR (LCD Control Register) ......................................................19 Bank 1 R6 LCDAR (LCD Address Register) .....................................................19 Bank 1 R7 LCDBR (LCD Data Buffer) ..............................................................20 Bank 1 R8 LCDVCR (LCD Voltage Control Register).......................................20 Bank 1 R9 LCDCCR (LCD Com Control Register 3) ........................................21 Bank 1 RA LCDSCR0 (LCD Segment Control Register 0) ...............................21 Bank 1 RB LCDSCR1 (LCD Segment Control Register 1) ...............................21 BANK 1 RC LCDSCR2 (LCD Segment Control Register 2) .............................22 Bank 1 RE EIMR (External Interrupt Mask Register)........................................22 Bank 1 RF EISR (External Interrupt Status Register) .......................................22 Bank 2 R5 T1CR (Timer 1 Control Register) ....................................................23 Bank 2 R6 TSR (Timer Status Register) ...........................................................24 Bank 2 R7 T1PD (Timer1 Period Buffer)...........................................................25 Bank 2 R8 T1TD (Timer 1 Duty Buffer) .............................................................25 * iii Register Operations ......................................................................................... 12 Product Specification (V0.9) 09.12.2006 Contents 6.2.31 6.2.32 6.2.33 6.2.34 6.2.35 6.2.36 6.2.37 6.2.38 6.2.39 6.2.40 6.2.41 6.2.42 6.2.43 6.2.44 6.2.45 6.2.46 6.2.47 6.2.48 6.2.49 6.2.50 6.2.51 6.2.52 6.2.53 6.2.54 6.2.55 6.2.56 6.2.57 6.2.58 6.2.59 6.2.60 6.2.61 6.2.62 6.2.63 6.2.64 6.2.65 6.2.66 6.2.67 6.2.68 6.2.69 6.2.70 6.2.71 6.2.72 Bank 2 R9 T2CR (Timer 2 Control Register) ....................................................25 Bank 2 RA T2PD (Timer 2 Period Buffer)..........................................................26 Bank 2 RB T2TD (Timer 2 Duty Buffer).............................................................26 Bank 2 RC SPIS (SPI Status Register) .............................................................26 Bank 2 RD SPIC (SPI Control Register) ...........................................................27 Bank 2 RE SPIR (SPI Read Buffer) ..................................................................28 Bank 2 RF SPIW (SPI Write Buffer) ..................................................................28 Bank 3 R5 URC (UART Control Register) ........................................................29 Bank 3 R6 URS (UART Status).........................................................................30 Bank 3 R7 URRD (UART_RD Data Buffer) ......................................................30 Bank 3 R8 URTD (UART_TD Data Buffer) .......................................................31 Bank 3 R9 ADCR (A/D Control Register) ..........................................................31 Bank 3 RA ADICH (A/D Input Control Register)................................................32 Bank 3 RB ADICL (A/D Input Control Register) ................................................32 Bank 3 RC ADDH (AD High 8-bit Data Buffer)..................................................32 Bank 3 RD ADDL (AD Low 4-bit Data Buffer) ...................................................32 Bank 3 RE EIESH (External Interrupt Edge Select High Byte Control Register).....33 Bank 3 RF EIESL (External Interrupt Edge Select Low Byte Control Register).......33 Bank 4 R5 LEDDCR (LED Drive Control Register)...........................................34 Bank 4 R6 WBCR (Watchdog Timer and Buzzer Control Register) ................34 Bank 4 R7 PIOCR (Port 7 I/O Control Register) ...............................................35 Bank 4 R8 PIOCR (Port 8 I/O Control Register) ...............................................35 Bank 4 R9 PIOCR (Port 9 I/O Control Register) ...............................................35 Bank 4 RA PIOCR (Port A I/O Control Register)...............................................35 Bank 4 RB PIOCR(Port B I/O Control Register) ...............................................36 Bank 4 RC PIOCR (Port C I/O Control Register)..............................................36 Bank 4 RF WKCR (Wake-up Control Register) ................................................36 Bank 5 R6 UARC2 (UART Control Register 2) .................................................36 Bank 5 R7 P7PHCR (Port 7 Pull High Control Register) ..................................37 Bank 5 R8 P8PHCR (Port 8 Pull High Control Register) ..................................37 Bank 5 R9 P9PHCR (Port 9 Pull-high Control Register)...................................37 Bank 5 RA PAPHCR (Port A Pull-high Control Register) ..................................37 Bank 5 RB PBPHCR (Port B Pull-high Control Register) .................................38 Bank 5 RC PCPHCR (Port C Pull High Control Register) ................................38 Bank 6 R6 LVRCR (Low Voltage Reset Control Register)................................38 Bank 6 R7 P7ODCR (Port 7 Open Drain Control Register)..............................38 Bank 6 R8 P8ODCR (Port 8 Open Drain Control Register)..............................39 Bank 6 R9 P9ODCR (Port 9 Open Drain Control Register)..............................39 Bank 6 RA PAODCR (Port A Open Drain Control Register) .............................39 Bank 6 RB PBODCR (Port B Open Drain Control Register).............................39 Bank 6 RC (Port C) ...........................................................................................39 R10~R3F (General Purpose Register)..............................................................39 6.3 TCC/WDT Pre-scaler........................................................................................ 40 iv * Product Specification (V0.9) 09.12.2006 Contents 6.4 6.5 6.6 I/O Port ............................................................................................................. 41 Reset and Wake-up.......................................................................................... 42 Oscillator .......................................................................................................... 52 6.6.1 6.6.2 6.6.3 6.6.4 Oscillator Modes................................................................................................52 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................52 RC Oscillator Mode with Internal Capacitor ......................................................54 Phase Lock Loop (PLL Mode)...........................................................................55 External Power-on Reset Circuit .......................................................................56 Residue-Voltage Protection...............................................................................57 6.7 Power-on Considerations ................................................................................. 56 6.7.1 6.7.2 6.8 6.9 Interrupt ............................................................................................................ 58 LCD Driver........................................................................................................ 59 6.9.1 6.9.2 6.9.3 6.9.4 R5 LCDCR (LCD Control Register)...................................................................60 R6 LCDADDR (LCD Address Register) ............................................................61 R7 LCDBR (LCD Data Buffer)...........................................................................62 R8 LCDVCR (LCD Voltage Control Register) ...................................................62 6.10 A/D Converter................................................................................................... 70 6.10.1 ADC Data Register............................................................................................71 6.10.2 A/D Sampling Time............................................................................................71 6.10.3 A/D Conversion Time ........................................................................................71 6.11 UART (Universal Asynchronous Receiver/Transmitter).................................... 72 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 UART Mode.......................................................................................................73 Transmitting.......................................................................................................74 Receiving...........................................................................................................74 Baud Rate Generator ........................................................................................75 UART Timing .....................................................................................................75 Overview & Features.........................................................................................76 SPI Function Description...................................................................................78 SPI Signal & Pin Description.............................................................................79 Programming the Related Registers .................................................................81 SPI Mode Timing ...............................................................................................84 Timer Mode .......................................................................................................86 T1OUT Mode.....................................................................................................86 Capture Mode....................................................................................................86 PWM Mode........................................................................................................87 16-Bit Mode .......................................................................................................87 6.12 SPI (Serial Peripheral Interface)....................................................................... 76 6.13 Timer/Counter 1................................................................................................ 85 6.14 Timer 2 ............................................................................................................. 88 6.14.1 Timer Mode .......................................................................................................89 6.14.2 PWM Mode........................................................................................................89 6.15 Code Options ................................................................................................... 90 6.16 Instruction Set .................................................................................................. 92 Product Specification (V0.9) 09.12.2006 *v Contents 7 8 Absolute Maximum Ratings ................................................................................... 95 DC Electrical Characteristics ................................................................................. 95 8.1 8.2 8.3 DC Electrical Characteristics............................................................................ 95 A/D Converter Characteristic............................................................................ 97 Phase Lock Loop Characteristic....................................................................... 98 8.3.1 8.3.2 PLL DC Electrical Characteristic .......................................................................98 AC Electrical Characteristic...............................................................................98 9 10 AC Electrical Characteristics ................................................................................. 99 Timing Diagrams ................................................................................................... 100 APPENDIX A B Package Type......................................................................................................... 101 Package Information............................................................................................. 101 B.1 48-Lead Low Profile Quad Flat Package (LQFP) ........................................... 101 B.2 44-Lead Low Profile Quad Flat Package (LQFP) ........................................... 102 B.3 44-Lead Quad Flat Package (QFP)................................................................ 103 B.4 42-Lead Dual Inline Package (DIP)................................................................ 104 B.5 32-Lead Shrink Dual Inline Package (SDIP) .................................................. 105 C D B.6 32-Lead Small Outline Package (SOP).......................................................... 106 EM78P510N Program Pin List .............................................................................. 107 ICE 510 Oscillator circuit (JP4) ............................................................................ 107 D.1 Mode1 ............................................................................................................ 107 D.2 Mode2 ............................................................................................................ 108 D.3 Mode3 ............................................................................................................ 108 D.4 Mode4 ............................................................................................................ 108 D.5 Mode5 ............................................................................................................ 109 D.6 Mode6 ............................................................................................................ 109 E D.7 Mode7 ............................................................................................................ 109 ICE 510 Output Pin Assignment (JP 3).................................................................110 Specification Revision History Doc. Version 1. 0.9 2. 3. Revision Description Preliminary version Modified sections 6-3 and 6-23 Modified the Operating Voltage 2006/09/12 Date vi * Product Specification (V0.9) 09.12.2006 EM78P510N 8-Bit Microcontrollers 1 General Description The EM78P510N is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. Integrated onto a single chip are on-chip Watchdog Timer (WDT), LCD Data RAM, ROM, programmable real time clock counter, internal/external interrupt, power down mode, 12 bits A/D Converter, UART, SPI, 8-channel LED driver, LCD driver and tri-state I/O. 2 Features Operating voltage: 2.3V5.5V Operating temperature:-40C~85C Dual clock operation or PLL operation mode Crystal/RC oscillation circuit selected by code option for system clock 32.768kHz crystal/RC oscillation circuit selected by code option for sub-oscillation Operation mode * * * * Normal mode Green mode Idle mode Sleep mode 272 bytes general purpose register 8Kx13 on-chip Electrical One Time Programmable Read Only Memory (OTP-ROM) 43 bidirectional tri-state I/O ports 8-level stacks for subroutine nesting 8-bit real time clock/counter (TCC) 8-bit Timer 1, auto reload counter/timer which can be interrupt sources * * * * * Timer Toggle output UART baud rate generator Capture PWM 8-bit Timer 2, auto reload counter/timer which can be interrupt sources * Timer * PWM * SPI baud rate generator Two sets of 8 bits auto reload counter/timer which can be cascaded to one 16-bit counter/timer Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) *1 EM78P510N 8-Bit Microcontrollers Programmable free running on chip watchdog timer Watch timer (1.0 sec / 0.5 sec / 0.25 sec / 3.91 ms) with Interrupt Buzzer Output (0.5K / 1K / 2K / 4K) Low Voltage Reset (2.6V / 3.3V / 3.9V) Low Voltage Detector (2.4V / 2.7V / 3.3V / 3.9V) 8-pin Direct Drive LED External Interrupt wake-up function 18 interrupt sources, 10 external, 8 internal 99.9% Single Instruction Cycle Commands LCD * * * * Common driver pins: 1, 3, 4, 8 Segment driver pins: 4, 8, 12, 16, 20, 23 1/2, 1/3, 1/4 bias Static 1/3, 1/4, 1/8 duty A/D Converter * 12-bit Converter resolution * 56s conversion speed at 1MHz fADC clock * 12-channel A/D Converter SPI (Serial Peripheral Interface) * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source UART: Universal Asynchronous Receiver/Transmitter * Three modes of transmit/receive * Allow the addition of a parity bit Package type: * * * * * * * * 2* 48-pin LQFP (7x7mm) 44-pin QFP (10x10mm) 42-pin DIP (600mil) 32-pin SDIP(400mil) 32-pin SDIP(400mil) 32-pin SOP (450mil) 32-pin SOP (450mil) : EM78P510NQ : EM78P510NBQ : EM78P510NP : EM78P510NK : EM78P510NAK : EM78P510NM : EM78P510NAM 44-pin LQFP (10x10mm) : EM78P510NAQ Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 3 Applications Remote control for air conditioner Health care Home appliance 4 Pin Assignment PB2/SEG10/INT6/AD11 37 36 35 34 33 32 48 P74/SEG18/INT0 P75/INT1/T1OUT/PWM1 P76/INT2/T1CK P77/INT3/T1CAP VDD VSS OSCO OSCI Test PC2/Xin PC3/Xout P81//RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 P82/INT8/AD8 47 46 45 44 43 42 41 40 39 38 PB3/SEG11/INT7 PC1/SEG22 PC0/SEG21 PB7/SEG20 PB6/SEG19 PB4/SEG16/RX PB5/SEG17/TX P72/SEG14 P71/SEG13 P73/SEG15 P70/SEG12 PB1/SEG9/INT5/AD10 PB0/SEG8/INT4/AD9 PA7/SEG7//SS PA6/SEG6/SCK PA5/SEG5/SO PA4/SEG4/SI PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 P97/COM0 P96/COM1 EM78P510NQ LQFP-48 31 30 29 28 27 26 25 14 P83/COM7/INT9/AD7 15 P84/VREF 16 P85/COM6/AD6 17 P86/COM5/AD5 18 P87/COM4/AD4 19 P90/AD3/PWM2 20 P91/AD2/BUZ 21 P92/AD1 22 P93/AD0 23 P94/COM3 24 P95/COM2 Figure 4-1a Pin Configuration for 48-pin LQFP Package Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) *3 EM78P510N 8-Bit Microcontrollers PB2/SEG10/INT6/AD11 PB1/SEG9/INT5/AD10 PB4/SEG16/RX PB3/SEG11/INT7 PB5/SEG17/TX PB0/SEG8/INT4/AD9 35 P73/SEG15 P71/SEG13 P74/SEG18/INT0 P75/INT1/T1OUT/PWM1 P76/INT2/T1CK P77/INT3/T1CAP VDD VSS OSCO OSCI Test PC2/Xin PC3/Xout 44 1 2 3 4 5 6 7 8 9 10 11 12 43 P72/SEG14 P70/SEG12 42 41 40 39 38 37 36 34 PA7/SEG7//SS 33 32 31 30 PA6/SEG6/SCK PA5/SEG5/SO PA4/SEG4/SI PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 P97/COM0 P96/COM1 P95/COM2 P94/COM3 EM78P510NAQ/BQ LQFP/QFP-44 29 28 27 26 25 24 23 13 14 P83/COM7/INT9/AD7 15 P84/VREF 16 P85/COM6/AD6 17 P86/COM5/AD5 18 P87/COM4/AD4 19 P90/AD3/PWM2 20 P91/AD2/BUZ 21 P92/AD1 22 P93/AD0 Figure 4-1b Pin Configuration for 44-pin LQFP/QFP Package 4* P82/INT8/AD8 P81//RESET Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers P70/SEG12 P71/SEG13 P72/SEG14 P73/SEG15 PB4/SEG16/RX PB5/SEG17/TX P74/SEG18/INT0 P75/INT1/T1OUT/PWM1 P76/INT2/T1CK P77/INT3/T1CAP VDD VSS OSCO OSCI Test PC2/Xin PC3/Xout P81//RESET P84/VREF P85/COM6/AD6 P86/COM5/AD5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 PB3/SEG11/INT7 PB2/SEG10/INT6/AD11 PB1/SEG9/INT5/AD10 PB0/SEG8/INT4/AD9 PA7/SEG7//SS PA6/SEG6/SCK PA5/SEG5/SO PA4/SEG4/SI PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 P97/COM0 P96/COM1 P95/COM2 P94/COM3 P93/AD0 P92/AD1 P91/AD2/BUZ P90/AD3/PWM2 P87/COM4/AD4 Figure 4-1c Pin Configuration for 42-pin DIP Package EM78P510NP DIP-42 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) *5 EM78P510N 8-Bit Microcontrollers VSS OSCO OSCI Test PC2/Xin PC3/Xout P81//RESET P84/VREF P90/AD3/PW2 P91/AD2/BUZ P92/AD1 P93/AD0 P94/COM3 P95/COM2 P96/COM1 P97/COM0 1 2 3 4 5 32 31 30 29 28 VDD P77/INT3/T1CAP P76/INT2/T1CK P75/INT1/T1OUT/PWM1 P74/SEG18/INT0 PB5/SEG17/TX PB4/SEG16/RX P73/SEG15 PB2/SEG10/INT6/AD11 PB1/SEG9/INT5/AD10 PB0/SEG8/INT4/AD9 PA7/SEG7//SS PA6/SEG6/SCK PA5/SEG5/SO PA4/SEG4/SI PA3/SEG3 EM78P510NK/M SDIP/SOP-32 EM78P510NAK/M SDIP/SOP-32 6 7 8 9 10 11 12 13 14 15 16 27 26 25 24 23 22 21 20 19 18 17 VSS OSCO OSCI Test PC2/Xin PC3/Xout P81//RESET P83/COM7/INT9/AD7 P84/VREF P90/AD3/PW2 P91/AD2/BUZ P92/AD1 P93/AD0 P94/COM3 P95/COM2 P96/COM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P77/INT3/T1CAP P76/INT2/T1CK P75/INT1/T1OUT/PWM1 P74/SEG18/INT0 PB5/SEG17/TX PB4/SEG16/RX P73/SEG15 PB2/SEG10/INT6/AD11 PB1/SEG9/INT5/AD10 PB0/SEG8/INT4/AD9 PA7/SEG7//SS PA6/SEG6/SCK PA5/SEG5/SO PA4/SEG4/SI P97/COM0 Figure 4-1d Pin Configuration for 32-pin skinny SDIP / SOP Package 6* Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 5 Pin Description Table 1 (a) LQFP-48 Pin Pin No. I/O Type Description 8-bit bidirectional I/O pins. P70 ~ P73 are pin-shared with SEG12 ~ SEG15, respectively. P74 is pin-shared with external Interrupt 0 or SEG18. P75 is pin-shared with external Interrupt 1 or T1OUT or PWM1. P76 is pin-shared with external Interrupt 2 or T1CK. P77 is pin-shared with external Interrupt 3 or T1CAP. 7-bit bidirectional I/O pins. P81 is pin-shared with RESET pin. P82 is pin-shared with Interrupt 8 or AD8 input. P83 is pin-shared with COM7 or Interrupt 9 or AD7 input. P84 is pin-shared with A/D reference input pin. P85 is pin-shared with COM6 or AD6 input. P86 is pin-shared with COM5 or AD5 input. P87 is pin-shared with COM4 or AD4 input. 8-bit bidirectional I/O pins. P90 is pin-shared with AD3 input or PWM2. P91 is pin-shared with AD2 input or BUZ. P92 ~P93 are pin-shared with AD1 ~ AD0 input, respectively. P94 ~P97 are pin-shared with COM3 ~ COM0, respectively. 8-bit bidirectional I/O pins. PA0 ~ PA3 are pin-shared with SEG0 ~ SEG3, respectively. PA4 is pin-shared with SEG4 or SPI SI pin. PA5 is pin-shared with SEG5 or SPI SO pin. PA6 is pin-shared with SEG6 or SPI SCK pin. PA7 is pin-shared with SEG7 or SPI /SS pin. 8-bit bidirectional I/O pins. PB0 is pin-shared with SEG8 or external Interrupt 4 or AD9 input. PB1 is pin-shared with SEG9 or external Interrupt 5 or AD10 input. PB2 is pin-shared with SEG10 or external Interrupt 6 or AD11 input. PB3 is pin-shared with SEG11 or external Interrupt 7. PB4 is pin-shared with SEG16 or UART RX pin. PB5 is pin-shared with SEG17 or UART TX pin. PB6 ~ PB7 are pin-shared with SEG19 ~ SEG20, respectively. 4-bit bidirectional I/O pins. PC0 ~ PC1 are pin-shared with SEG21 ~ SEG22, respectively. PC2 ~PC3 are pin-shared with Xin ~ Xout, respectively. Crystal mode: crystal input RC mode: pull-high resistor PLL mode: connect 0.01F capacitance to GND. Connect 0.01F capacitor to GND and code option select PLL mode when high oscillator is not used. Crystal mode: crystal output RC mode: instruction clock output PLL mode: instruction clock output Test signal import pin (must be connected to VDD) Crystal mode: input pin for sub-oscillator. Connect to a 32.768kHz crystal. RC mode: pull-high resistor In crystal mode: connect to a 32.768kHz crystal. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in rest condition. Power supply pin System ground pin P70~P77 1~4, 39~42 I/O P81~P87 12~18 I/O P90~P97 19~26 I/O PA0~PA7 27~34 I/O PB0~PB7 35~38, 43~46 I/O PC0~PC3 47~48 10~11 I/O OSCI 8 I OSCO Test Xin Xout /RESET VDD VSS 7 9 10 11 12 5 6 O I I O I I I Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) *7 EM78P510N 8-Bit Microcontrollers Table 1 (b) LQFP-44/QFP-44 Pin Pin No. I/O Type Description 8-bit bidirectional I/O pins. P70 ~ P73 are pin-shared with SEG12 ~ SEG15, respectively. P74 is pin-shared with external Interrupt 0 or SEG18. P75 is pin-shared with external Interrupt 1 or T1OUT or PWM1. P76 is pin-shared with external Interrupt 2 or T1CK. P77 is pin-shared with external Interrupt 3 or T1CAP. 7-bit bidirectional I/O pins. P81 is pin-shared with RESET pin. P82 is pin-shared with Interrupt 8 or AD8 input. P83 is pin-shared with COM7 or Interrupt 9 or AD7 input. P84 is pin-shared with A/D reference input pin. P85 is pin-shared with COM6 or AD6 input. P86 is pin-shared with COM5 or AD5 input. P87 is pin-shared with COM4 or AD4 input. 8-bit bidirectional I/O pins. P90 is pin-shared with AD3 input or PWM2. P91 is pin-shared with AD2 input or BUZ. P92 ~P93 are pin-shared with AD1 ~ AD0 input, respectively. P94 ~P97 are pin-shared with COM3 ~ COM0, respectively. 8-bit bidirectional I/O pins. PA0 ~ PA3 are pin-shared with SEG0 ~ SEG3, respectively. PA4 is pin-shared with SEG4 or SPI SI pin. PA5 is pin-shared with SEG5 or SPI SO pin. PA6 is pin-shared with SEG6 or SPI SCK pin. PA7 is pin-shared with SEG7 or SPI /SS pin. 6-bit bidirectional I/O pins. PB0 is pin-shared with SEG8 or external Interrupt 4 or AD9 input. PB1 is pin-shared with SEG9 or external Interrupt 5 or AD10 input. PB2 is pin-shared with SEG10 or external Interrupt 6 or AD11 input. PB3 is pin-shared with SEG11 or external Interrupt 7. PB4 is pin-shared with SEG16 or UART RX pin. PB5 is pin-shared with SEG17 or UART TX pin. 2-bit bidirectional I/O pins. PC2 ~PC3 are pin-shared with Xin ~ Xout, respectively. Crystal mode: crystal input RC mode: pull-high resistor PLL mode: connect 0.01F capacitance to GND. Connect 0.01F capacitor to GND and code option select PLL mode when high oscillator is not used. Crystal mode: crystal output RC mode: instruction clock output PLL mode: instruction clock output Test signal import pin (must be connected to VDD) Crystal mode: input pin for sub-oscillator. Connect to a 32.768kHz crystal. RC mode: pull-high resistor Crystal mode: connect to a 32.768kHz crystal. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply pin System ground pin P70~P77 1~4, 39~42 I/O P81~P87 12~18 I/O P90~P97 19~26 I/O PA0~PA7 27~34 I/O PB0~PB5 35~38, 43~44 I/O PC2~PC3 10~11 I/O OSCI 8 I OSCO Test Xin Xout /RESET VDD VSS 7 9 10 11 12 5 6 O I I O I I I 8* Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Table 1 (c) DIP-42 Pin Pin No. I/O Type 8-bit bidirectional I/O pins. P70 ~ P73 are pin-shared with SEG12 ~ SEG15, respectively. P70~P77 1~4, 7~10 I/O P74 is pin-shared with external Interrupt 0 or SEG18. P75 is pin-shared with external Interrupt 1 or T1OUT or PWM1. P76 is pin-shared with external Interrupt 2 or T1CK. P77 is pin-shared with external Interrupt 3 or T1CAP. 5-bit bidirectional I/O pins. P81 is pin-shared with RESET pin. P81 P84~P87 18~22 I/O P84 is pin-shared with A/D reference input pin. P85 is pin-shared with COM6 or AD6 input. P86 is pin-shared with COM5 or AD5 input. P87 is pin-shared with COM4 or AD4 input. 8-bit bidirectional I/O pins. P90 is pin-shared with AD3 input or PWM2. P91 is pin-shared with AD2 input or BUZ. P92 ~P93 are pin-shared with AD1 ~ AD0 input, respectively. P94 ~P97 are pin-shared with COM3 ~ COM0, respectively. 8-bit bidirectional I/O pins. PA0 ~ PA3 are pin-shared with SEG0 ~ SEG3, respectively. PA4 is pin-shared with SEG4 or SPI SI pin. PA5 is pin-shared with SEG5 or SPI SO pin. PA6 is pin-shared with SEG6 or SPI SCK pin. PA7 is pin-shared with SEG7 or SPI /SS pin. 6-bit bidirectional I/O pins. PB0 is pin-shared with SEG8 or external Interrupt 4 or AD9 input. PB1 is pin-shared with SEG9 or external Interrupt 5 or AD10 input. PB2 is pin-shared with SEG10 or external Interrupt 6 or AD11 input. PB3 is pin-shared with SEG11 or external Interrupt 7. PB4 is pin-shared with SEG16 or UART RX pin. PB5 is pin-shared with SEG17 or UART TX pin. 2-bit bidirectional I/O pins. PC2 ~PC3 are pin-shared with Xin ~ Xout, respectively. Crystal mode: crystal input RC mode: pull-high resistor PLL mode: connect 0.01F capacitance to GND. Connect 0.01F capacitor to GND and code option select PLL mode when high oscillator is not used. Crystal mode: crystal output RC mode: instruction clock output PLL mode: instruction clock output Test signal import pin (must be connected to VDD) Crystal mode: input pin for sub-oscillator. Connect to a 32.768kHz crystal. RC mode: pull-high resistor Crystal mode: connect to a 32.768kHz crystal. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply pin System ground pin *9 Description P90~P97 23~30 I/O PA0~PA7 31~38 I/O PB0~PB5 39~42, 5~6 I/O PC2~PC3 16~17 I/O OSCI 14 I OSCO Test Xin Xout /RESET VDD VSS 13 15 16 17 18 11 12 O I I O I I I Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Table 1 (d) SDIP-32/SOP-32 Pin Pin No. I/O Type 5-bit bidirectional I/O pins. P73 is pin-shared with SEG15. P73, P74~P77 25, 28~31 I/O P74 is pin-shared with external Interrupt 0 or SEG18. P75 is pin-shared with external Interrupt 1 or T1OUT or PWM1. P76 is pin-shared with external Interrupt 2 or T1CK. P77 is pin-shared with external Interrupt 3 or T1CAP. 2-bit bidirectional I/O pins. P81//RESET P84/VREF 7 8 P81 is pin-shared with RESET pin. I/O P83 can be used as COM7 or Interrupt 9 or AD7 input.(for EM78P510NAK/M use only) P84 is pin-shared with A/D reference input pin. 8-bit bidirectional I/O pins. P90 is pin-shared with AD3 input or PWM2. P91 is pin-shared with AD2 input or BUZ. P92 ~P93 are pin-shared with AD1 ~ AD0 input, respectively. P94 ~P97 are pin-shared with COM3 ~ COM0, respectively. 5-bit bidirectional I/O pins. PA3 is pin-shared with SEG3 (for EM78P510NK/M only) PA4 is pin-shared with SEG4 or SPI SI pin. PA5 is pin-shared with SEG5 or SPI SO pin. PA6 is pin-shared with SEG6 or SPI SCK pin. PA7 is pin-shared with SEG7 or SPI /SS pin. 5-bit bidirectional I/O pins. PB0 is pin-shared with SEG8 or external Interrupt 4 or AD9 input. PB1 is pin-shared with SEG9 or external Interrupt 5 or AD10 input. PB2 is pin-shared with SEG10 or external Interrupt 6 or AD11 input. PB3 is pin-shared with SEG11 or external Interrupt 7. PB4 is pin-shared with SEG16 or UART RX pin. PB5 is pin-shared with SEG17 or UART TX pin. 2-bit bidirectional I/O pins. PC2 ~PC3 are pin-shared with Xin ~ Xout, respectively. Crystal mode: crystal input RC mode: pull-high resistor PLL mode: connect 0.01F capacitance to GND. Connect 0.01F capacitor to GND and code option select PLL mode when high oscillator is not used. Crystal mode: crystal output RC mode: instruction clock output PLL mode: instruction clock output Test signal import pin (must be connected to VDD) Crystal mode: input pin for sub-oscillator. Connect to a 32.768kHz crystal. RC mode: pull-high resistor Crystal mode: connect to a 32.768kHz crystal. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply pin System ground pin Description P90~P97 23~30 I/O PA3~PA7 17~21 I/O PB0~PB2 PB4~PB5 22~24, 26~27 I/O PC2~PC3 5~6 I/O OSCI 3 I OSCO Test Xin Xout /RESET VDD VSS 2 45 5 6 7 32 1 O I I O I I I 10 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 5 Functional Block Diagram CPU L C D d r iv e r LC D T im in g C o n tr o l IO P O R T IO T im e r / C o u n te r PW M ROM A /D C o n v e r te r SPI UART BUZZY LVR LVD Figure 5-1a EM78P510N Block Diagram (Overview) Figure 5-1b EM78P510N Block Diagram (Detailed) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 11 EM78P510N 8-Bit Microcontrollers 6 Function Description 6.1 Register Configuration 6.1.1 R PAGE Register Configuration Bank0 R0 ( IAR ) R1 ( TCC ) R2 ( PC ) R3 (SR) R4 ( RSR ) RBSR RPSR PORT7 PORT8 PORT9 PORTA PORTB SCCR TWTCR IMR ISR R10 R20 R3F . . . . Bank7 R20 R3F EIMR EISR LCDCR LCDAR LCDBR LCDVCR LCDCCR LCDSCR0 LCDSCR1 LCDSCR2 T1CR TSR T1PD T1TD T2CR T2PD T2TD SPIS SPIC SPIR SPIW URC URS URRD URTD ADCR ADICH ADICL ADDH ADDL EIESH EIESL WKCR LEDDCR WBCR IOC7 IOC8 IOC9 IOCA IOCB IOCC URC2 P7PHCR P8PHCR P9PHCR PAPHCR PBPHCR PCPHCR LVRCR P7ODCR P8ODCR P9ODCR PAODCR PBODCR PORTC Bank1 Bank2 Bank3 Bank4 Bank5 Bank6 General Purpose Ram Figure 6-1 Data memory Configuration 6.2 Register Operations 6.2.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). 6.2.2 R1 (TCC) Incremented by the main oscillator clock (Fm) or sub oscillator clock (Fs) (controlled by TWTCR register). Written and read by the program as any other register. 6.2.3 R2 (Program Counter) The structure is depicted in Fig. 6-2. Generates 8K x 13 on-chip ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. 12 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers "CALL" instruction loads the low 10 bits of the PC and PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and contents of the ninth and tenth bits don't change. "ADD R2, A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A11) will be loaded with the contents of Bit PS0~PS2 in the status register (R6) upon the execution of a "JMP'', "CALL'' instruction. Figure 6-2 Program Counter Organization User can use Long jump (LJMP) or long call (LCALL) instructions to program user's code. And the program page is maintained by ELAN's compiler. It will change user's program by inserting instructions within the program. 6.2.4 R3 (Status, Page Selection) Status Flag, Page Selection Bits Bit 7 LVDEN Bit 6 LVDS1 Bit 5 LVDS0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C Bit 7 (LVDEN): Voltage Detect Enable Bit 0 : No action 1 : Voltage detect enabled Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 13 EM78P510N 8-Bit Microcontrollers Bits 6~5 (LVDS1~LVDS0): Detect Voltage Select Bits LVDS1 0 0 1 1 LVDS0 0 1 0 1 Detect Voltage 2.4V 2.7V 3.3V 3.9V Bit 4 (T): Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. Bit 3 (P): Power down bit Set to "1" during power on or by a "WDTC" command and reset to "0" by a "SLEP" command. Event WDT wakes up from sleep mode WDT times out (not in sleep mode) /RESET wakes up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 x x = don't care Remarks Bit 2 (Z): Zero flag Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 6.2.5 R4 (RAM Select Register) Bit 7 (VDB): Voltage Detector. This is a read only bit. When VDD pin voltage is lower then Vdet (select by LVDS0~LVDS1) this bit will be cleared. 0 : low voltage is detected 1 : low voltage is not detected or LVD function is disabled Bit 6 (BNC): Bank Control Register. 0 : allow to access only Bank 0 registers 1 : Allow to access all registers of any Bank Bits 5~0: are used to select up to 64 registers in the indirect addressing mode. See the configuration of the data memory. User can use BANK instruction to change bank. 14 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.6 Bank 0 R5 (RAM Bank Select Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 BS2 Bit 1 BS1 Bit 0 BS0 Bits 7~3: Reserved Bits 2~0 (BS2~BS0): RAM Bank Select Register BS2 0 0 : : 1 BS1 0 0 : : 1 BS0 0 1 : : 1 RAM Bank Bank 0 Bank 1 : : Bank 7 6.2.7 Bank 0 R6 (Program Page Select Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 PS2 Bit 1 PS1 Bit 0 PS0 Bits 7~3: Reserved Bits 2~0 (PS2~PS0): ROM Page Select Register PS2 0 0 : : 1 PS1 0 0 : : 1 PS0 0 1 : : 1 ROM PAGE Page 0 Page 1 : : Page 7 6.2.8 Bank 0 R7 (Port 7) Bit 7 R77 Bit 6 R76 Bit 5 R75 Bit 4 R74 Bit 3 R73 Bit 2 R72 Bit 1 R71 Bit 0 R70 Bits 7~0 (R77~R70): Port 7 8-bit I/O Registers. 6.2.9 Bank 0 R8 (Port 8) Bit 7 R87 Bit 6 R86 Bit 5 R85 Bit 4 R84 Bit 3 R83 Bit 2 R82 Bit 1 R81 Bit 0 0 Bits 7~1 (R87~R81): Port 8 7-bit I/O Registers. Bit 0: Reserved Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 15 EM78P510N 8-Bit Microcontrollers 6.2.10 Bank 0 R9 (Port 9) Bit 7 R97 Bit 6 R96 Bit 5 R95 Bit 4 R94 Bit 3 R93 Bit 2 R92 Bit 1 R91 Bit 0 R90 Bits 7~0 (R97~R90): Port 9 8-bit I/O Registers. 6.2.11 Bank 0 RA (Port A) Bit 7 RA7 Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Bits 7~0 (RA7~RA0): Port A 8-bit I/O Registers 6.2.12 Bank 0 RB (Port B) Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Bits 7~0 (RB7~RB0): Port B 8-bit I/O Registers 6.2.13 Bank 0 RC SCCR (System Clock Control Register) Bit 7 0 Bit 6 CLK2 Bit 5 CLK1 Bit 4 CLK0 Bit 3 IDLE Bit 2 0 Bit 1 0 Bit 0 CPUS Bit 7: Reserved, fixed to "0" Bits 6~4 (CLK2~CLK0): Main Clock Select Bit for PLL Mode (code option select) CLK2 0 0 0 0 1 1 1 CLK1 0 0 1 1 0 0 1 CLK0 0 1 0 1 0 1 x Main Clock Fsx122 Fsx61 Fsx61/2 Fsx61/4 Fsx244 Fsx366 Fsx488 Ex: Fs=32.768K 3.997 MHz 1.998 MHz 0.999 MHz 499.7 kHz 7.995 MHz 11.99 MHz 15.99 MHz Bit 3 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode to go. IDLE="0"+SLEP instruction sleep mode IDLE="1"+SLEP instruction idle mode Bits 2~1: Reserved, fixed to "0" Bit 0 (CPUS): CPU Oscillator Source Select, 0/1 sub-oscillator (fs)/ main oscillator (fosc)When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped. 16 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers CPU Operation Mode Figure 6-3 CPU operation mode 6.2.14 Bank 0 RD TWTCR (TCC and WDT Timer Control Register) Bit 7 WDTE Bit 6 WPSR2 Bit 5 WPSR1 Bit 4 WPSR0 Bit 3 TCCS Bit 2 TPSR2 Bit 1 TPSR1 Bit 0 TPSR0 Bit 7 (WDTE): Watchdog Timer Enable. This control bit is used to enable the watchdog timer. 0 : Disable WDT function 1 : Enable WDT function Bits 6~4 (WPSR2~WPSR0): WDT Prescaler Bits WPSR2 0 0 0 0 1 1 1 1 WPSR1 0 0 1 1 0 0 1 1 WPSR0 0 1 0 1 0 1 0 1 Prescaler 1:1 (Default) 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Bit 3 (TCCS): TCC Clock Source Select Bit 0 : Fm (main clock). 1 : Fs (sub clock: 32.768kHz) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 17 EM78P510N 8-Bit Microcontrollers Bits 2~0 (TPSR2~TPSR0): TCC Prescaler Bits TPSR2 0 0 0 0 1 1 1 1 TPSR1 0 0 1 1 0 0 1 1 TPSR0 0 1 0 1 0 1 0 1 Prescaler 1:2 (Default) 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 6.2.15 Bank 0 RE IMR (Interrupt Mask Register) Bit 7 T1IE Bit 6 LVDIE Bit 5 ADIE Bit 4 SPIE Bit 3 URTIE Bit 2 EXIE9 Bit 1 EXIE8 Bit 0 TCIE Bits 7~0 (T1IE~TCIE): Interrupt Enable Bit. Enable interrupt source respectively. 0 : Disable interrupt 1 : Enable interrupt External Interrupt INT pin INT8 INT9 Secondary function Pin P82, AD8 P83, COM7, AD7 Enable Condition ENI+EXIE8(IMR1) ENI+EXIE9(IMR2) Edge Rising or Falling Rising or Falling Digital Noise Reject 2/Fc 2/Fc INT8~INT9: Pulse less then 2/Fc is eliminated as noise. Pulse less then 5/Fc is eliminated as noise. 6.2.16 Bank 0 RF ISR (Interrupt Status Register) Bit 7 T1IF Bit 6 LVDIF Bit 5 ADIF Bit 4 SPIF Bit 3 URTIF Bit 2 EXIF9 Bit 1 EXIF8 Bit 0 TCIF These bits are set to "1" when interrupt occurs respectively. Bit 7 (T1IF): Interrupt Flag of Timer 1 Interrupt Bit 6 (LVDIF): Interrupt Flag of Low Voltage Detector Interrupt Bit 5 (ADIF): Interrupt Flag of A/D Convert Complete Bit 4 (SPIIF): Interrupt Flag of SPI Transfer Complete Bit 3 (URTIF): Interrupt Flag of UART Transfer Complete Bit 2 (EXIF9): Interrupt Flag of External Interrupt 9 occurs Bit 1 (EXIF8): Interrupt Flag of External Interrupt 8 occurs. Bit 0 (TCIF): Interrupt Flag of TCC overflow 18 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.17 Bank 1 R5 LCDCR (LCD Control Register) Bit 7 LCDEN Bit 6 LCDTYPE Bit 5 BS1 Bit 4 BS0 Bit 3 DS1 Bit 2 DS0 Bit 1 LCDF1 Bit 0 LCDF0 Bit 7 (LCDEN): LCD Enable Select Bit 0 : LCD disabled. All common/segment outputs are set to VDD level. 1 : LCD enabled Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit 0 : A type wave 1 : B type wave Bits 5~4 (BS1~BS0): LCD Bias Select Bits BS1 0 0 1 BS0 0 1 X LCD Bias Select 1/2 Bias 1/3 Bias 1/4 Bias Bits 3~2 (DS1~DS0): LCD Duty Select Bits DS1 0 0 1 1 DS0 0 1 0 1 LCD Duty Static 1/3 Duty 1/4 Duty 1/8 Duty Bits 1~0 (LCDF1~LCDF0): LCD Frame Frequency Control Bits LCD Frame Frequency (e.q. Fs=32.768K) LCDF1 LCDF0 0 0 1 1 0 1 0 1 Static Fs/(512x1) = 64.0 Fs/(560x1) = 58.5 Fs/(608x1) = 53.9 Fs/(464x1) = 70.6 1/3 Duty Fs/(172x3) =63.5 Fs/(188x3) = 58 1/4 Duty Fs/(128x4) = 64 Fs/(140x4) = 58.5 1/8 Duty Fs/(64x8) = 64.0 Fs/(70x8) = 58.5 Fs/(76x8) = 53.9 Fs/(58x8) = 70.6 Fs/(204x3) = 53.5 Fs/(152x4) = 53.9 Fs/(156x3) = 70 Fs/(116x4) = 70.6 6.2.18 Bank 1 R6 LCDAR (LCD Address Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 LCD_A4 Bit 3 LCD_A3 Bit 2 LCD_A2 Bit 1 LCD_A1 Bit 0 LCD_A0 Bits 7~5: Reserved Bits 4~0 (LCD_A4~LCD_A0): LCD RAM Address Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 19 EM78P510N 8-Bit Microcontrollers R6 R7 (LCD Data Buffer) Segment (LCD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address) (LCD_D7) (LCD_D6) (LCD_D5) (LCD_D4) (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0) 00H 01H 02H | 14H 15H 16H Common COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 | SEG20 SEG21 SEG22 6.2.19 Bank 1 R7 LCDBR (LCD Data Buffer) Bit 7 LCD_D 7 Bit 6 LCD_D 6 Bit 5 LCD_D 5 Bit 4 LCD_D 4 Bit 3 LCD_D 3 Bit 2 LCD_D 2 Bit 1 LCD_D 1 Bit 0 LCD_D 0 Bit 7~0 (LCD_D7~LCD_D0): LCD RAM Data Transfer Register 6.2.20 Bank 1 R8 LCDVCR (LCD Voltage Control Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 LCDC1 Bit 3 LCDC0 Bit 2 LCDVC2 Bit 1 LCDVC1 Bit 0 LCDVC0 Bits 7~5: Reserved Bits 4~3 (LCDC1~LCDC0): LCD Clock LCDC1 0 0 1 1 LCDC0 0 1 0 1 Fm 16M 8M 4M 2M FLCD Fc/29 Fc/28 Fc/27 Fc/26 When the main oscillator operates in crystal mode and the sub-oscillator does not, it's a must to set these two bits for the LCD clock. 20 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bits 2~0 (LCDVC2~LCDVC0): LCD Voltage Control Bits LCDVC2 0 0 0 0 1 1 1 1 LCDVC1 0 0 1 1 0 0 1 1 LCDVC0 0 1 0 1 0 1 0 1 Output 0.4VDD ~ VDD 0.34VDD ~ VDD 0.26VDD ~ VDD 0.18VDD ~ VDD 0.13VDD ~ VDD 0.07VDD ~ VDD 0.04VDD ~ VDD 0V ~ VDD 6.2.21 Bank 1 R9 LCDCCR (LCD Com Control Register 3) Bit 7 COM7 Bit 6 COM6 Bit 5 COM5 Bit 4 COM4 Bit 3 COM3 Bit 2 COM2 Bit 1 COM1 Bit 0 COM0 Bits 7~0 (COM7~COM0): LCD Com 7~0 Control Bits 0 : Disable, functions as normal I/O or other functions 1 : Enable, functions as LCD common driver pins 6.2.22 Bank 1 RA LCDSCR0 (LCD Segment Control Register 0) Bit 7 SEG7 Bit 6 SEG6 Bit 5 SEG5 Bit 4 SEG4 Bit 3 SEG3 Bit 2 SEG2 Bit 1 SEG1 Bit 0 SEG0 Bits 7~0 (SEG7~SEG0): LCD Segments 7~0 Control Bits 0 : Disable, functions as normal I/O or other functions 1 : Enable, functions as LCD common driver pins 6.2.23 Bank 1 RB LCDSCR1 (LCD Segment Control Register 1) Bit 7 SEG15 Bit 6 SEG14 Bit 5 SEG13 Bit 4 SEG12 Bit 3 SEG11 Bit 2 SEG10 Bit 1 SEG9 Bit 0 SEG8 Bits 7~0 (SEG15~SEG8): LCD Segments 15~8 Control Bits 0 : Disable, functions as normal I/O or other functions 1 : Enable, functions as LCD common driver pins Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 21 EM78P510N 8-Bit Microcontrollers 6.2.24 Bank 1 RC LCDSCR2 (LCD Segment Control Register 2) Bit 7 Bit 6 SEG22 Bit 5 SEG21 Bit 4 SEG20 Bit 3 SEG19 Bit 2 SEG18 Bit 1 SEG17 Bit 0 SEG16 Bit 7: Reserved Bits 6~0 (SEG22~SEG16): LCD Segment 22~16 Control Bits 0 : Disable, functions as normal I/O or other functions 1 : Enable, functions as LCD common driver pins 6.2.25 Bank 1 RE EIMR (External Interrupt Mask Register) Bit 7 EXIE7 Bit 6 EXIE6 Bit 5 EXIE5 Bit 4 EXIE4 Bit 3 EXIE3 Bit 2 EXIE2 Bit 1 EXIE1 Bit 0 EXIE0 Bits 7~0 (EXIE7~EXIE0): Interrupt Enable Bit. Enable interrupt source respectively. External interrupt INT Pin Secondary Function Pin INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 PB3, SEG11 PB2, SEG10, AD11 PB1, SEG9, AD10 PB0, SEG8, AD9 P77, T1CAP P76, T1CK P75, T1OUT, PWM1 P74, SEG18 Enable Condition ENI+EXIE7(EIMR7) ENI+EXIE6(EIMR6) ENI+EXIE5(EIMR5) ENI+EXIE4(EIMR4) ENI+EXIE3(EIMR3) ENI+EXIE2(EIMR2) ENI+EXIE1(EIMR1) ENI+EXIE0(EIMR0) Edge Rising or Falling Rising or Falling Rising or Falling Rising or Falling Rising or Falling Rising or Falling Rising or Falling Rising or Falling Digital Noise Reject 2/Fc 2/Fc 2/Fc 2/Fc 2/Fc 2/Fc 2/Fc 2/Fc INT7~INT0: Pulse less than 2/Fc is eliminated as noise. Pulse less than 5/Fc is eliminated as noise. 6.2.26 Bank 1 RF EISR (External Interrupt Status Register) Bit 7 EXIF7 Bit 6 EXIF6 Bit 5 EXIF5 Bit 4 EXIF4 Bit 3 EXIF3 Bit 2 EXIF2 Bit 1 EXIF1 Bit 0 EXIF0 These bits are set to "1" when interrupt occurs respectively. Bits 7~0 (EXIF7~EXIF0): Interrupt Flag when External Interrupt 7~0 occur 22 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.27 Bank 2 R5 T1CR (Timer1 Control Register) Bit 7 TIS1 Bit 6 TIS0 Bit 5 T1MS2 Bit 4 T1MS1 Bit 3 T1MS0 Bit 2 T1P2 Bit 1 T1P1 Bit 0 T1P0 Bits 7~6 (TIS1~ TIS0): Timer 1 and Timer 2 Interrupt Type Select Bits. These two bits are used when the Timer operates in PWM mode. TIS1 0 0 1 TIS0 0 1 X Timer 1 and Timer 2 Interrupt Type Select T1PD underflow T1TD underflow T1PD and T1TD underflow Bits 5~3 (T1MS2~T1MS0): Timer 1 Operation Mode Select Bits T1MS2 0 0 0 0 1 1 1 1 T1MS1 0 0 1 1 0 0 1 1 T1MS0 0 1 0 1 0 1 0 1 PWM 1 Timer 1 Mode Select Timer 1 T1OUT Mode Capture Mode Rising Edge Capture Mode Falling Edge UART Baud Rate Generator Bits 2~0 (T1P2~T1P0): Timer 1 Prescaler Bits T1P2 0 0 0 0 1 1 1 1 T1P1 0 0 1 1 0 0 1 1 T1P0 0 1 0 1 0 1 0 1 Prescaler 1:2 (Default) 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 23 EM78P510N 8-Bit Microcontrollers 6.2.28 Bank 2 R6 TSR (Timer Status Register) Bit 7 T1MOD Bit 6 TRCB Bit 5 T1CSS1 Bit 4 T1CSS0 Bit 3 T2CSS Bit 2 T1EN Bit 1 T1OMS Bit 0 T1OC Bit 7 (T1MOD): Timer Operates Mode Select Bit 0 : Two 8-bit Timer 1 : Timer 1 and Timer 2 cascade to one 16-bit Timer NOTE By setting T1MOD to "1", Timer can cascade to one 16-bit Timer. This 16 bits Timer is controlled by Time r1, including enable, clock source and prescaler. Timer 1 is MSB and Timer 2 is LSB in value of period and duty. Bit 6 (TRCB): Timers 1, 2 Read Control Bit 0: When this bit set to 0, read data from T1PD or T2PD. 1: When this bit set to 1, read data from T1PD or T2PD, but this is value of timer counter. Bits 5~4 (T1CSS1~T1CSS0): Timer 1 Clock Source Select Bits T1CSS1 0 0 1 T1CSS0 0 1 X Timer 1 Clock Source Select Fm Fs T1CK Bit 3 (T2CSS): Timer 2 Clock Source Select Bit 0 : Main clock with prescaler 1 : Sub clock with prescaler Bit 2 (T1EN): Timer 1 Start Bit 0 : Timer 1 stop 1 : Timer 1 start Bit 1 (T1OMS): Timer 1 Output Mode Select Bit 0 : Repeating mode 1 : One-shot mode NOTE One-shot mode is only used in Timer 1, Capture and PWM1 modes. 24 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Mode Selected Timer 1 Description Down-counter wills underflow once and can't auto reload from T1PD. In this mode, period and duty of the T1CAP input pin are measured once. This moment free running counter stop and can't detect a change of T1CAP edge. In this mode will generate one set of PWM1's duty and period, and then free running counter will stop. Capture PWM1 Bit 0 (T1OC): Timer1 Output Flip-Flop Control Bit 0 : T-FF is low 1 : T-FF is high 6.2.29 Bank 2 R7 T1PD (Timer1 Period Buffer) Bit 7 PRD1[7] Bit 6 PRD1[6] Bit 5 PRD1[5] Bit 4 PRD1[4] Bit 3 PRD1[3] Bit 2 PRD1[2] Bit 1 PRD1[1] Bit 0 PRD1[0] Bits 7~0 (PRD1[7]~PRD1[0]): The content of this register is a period of Timer 1. 6.2.30 Bank 2 R8 T1TD (Timer 1 Duty Buffer) Bit 7 TD1[7] Bit 6 TD1[6] Bit 5 TD1[5] Bit 4 TD1[4] Bit 3 TD1[3] Bit 2 TD1[2] Bit 1 TD1[1] Bit 0 TD1[0] Bits 7~0 (TD1[7]~TD1[0]): The content of this register is a duty of Timer 1. 6.2.31 Bank 2 R9 T2CR (Timer 2 Control Register) Bit 7 T2IF Bit 6 T2IE Bit 5 T2EN Bit 4 T2MS1 Bit 3 T2MS0 Bit 2 T2P2 Bit 1 T2P1 Bit 0 T2P0 Bit 7 (T2IF): Interrupt Flag of Timer 2 Interrupt Bit 6 (T2IE): Timer 2 Interrupt Mask Bit 0 : Disable Timer 2 interrupt 1 : Enable Timer 2 interrupt Bit 5 (T2EN): Timer 2 Start Bit 0 : Timer 2 stop 1 : Timer 2 start Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 25 EM78P510N 8-Bit Microcontrollers Bits 4~3 (T2MS1~T2MS0): Timer 2 Operation Mode Selects Bits T2MS1 0 0 1 1 T2MS0 0 1 0 1 Timer 2 Mode Select Timer 2 SPI Baud Rate Generator PWM 2 Bits 2~0 (T2P2~T2P0): Timer 2 Prescaler Bits T2P2 0 0 0 0 1 1 1 1 T2P1 0 0 1 1 0 0 1 1 T2P0 0 1 0 1 0 1 0 1 Prescaler 1:2 (Default) 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 6.2.32 Bank 2 RA T2PD (Timer 2 Period Buffer) Bit 7 PRD2[7] Bit 6 PRD2[6] Bit 5 PRD2[5] Bit 4 PRD2[4] Bit 3 PRD2[3] Bit 2 PRD2[2] Bit 1 PRD2[1] Bit 0 PRD2[0] Bits 7~0 (PRD2[7]~PRD2[0]): The content of this register is a period of Timer2. 6.2.33 Bank 2 RB T2TD (Timer 2 Duty Buffer) Bit 7 TD2[7] Bit 6 TD2[6] Bit 5 TD2[5] Bit 4 TD2[4] Bit 3 TD2[3] Bit 2 TD2[2] Bit 1 TD2[1] Bit 0 TD2[0] Bits 7~0 (TD2[7]~TD2[0]): The contents of this register is a duty of Timer 2. 6.2.34 Bank 2 RC SPIS (SPI Status Register) Bit 7 DORD Bit 6 TD1 Bit 5 TD0 Bit 4 0 Bit 3 OD3 Bit 2 OD4 Bit 1 0 Bit 0 RBF Bit 7 (DORD): Data Shift Control Bit 0 : Shift left (MSB first) 1 : Shift right (LSB first) 26 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options TD1 0 0 1 1 TD0 0 1 0 1 Delay Time 8 CLK 16 CLK 24 CLK 32 CLK Bit 4: Reserved Bit 3 (OD3): Open-Drain Control Bit 1 : Open-drain enable for SDO 0 : Open-drain disable for SDO Bit 2 (OD4): Open-Drain Control bit 1 : Open-drain enable for SCK 0 : Open-drain disable for SCK Bit 1: Reserved Bit 0 (RBF): Read Buffer Full Flag 1 : Receiving completed, and SPIRB is fully exchanged. 0 : Receiving not completed, and SPIRB has not fully exchanged. 6.2.35 Bank 2 RD SPIC (SPI Control Register) Bit 7 CES Bit 6 SPIE Bit 5 SRO Bit 4 SSE Bit 3 SDOC Bit 2 SBRS2 Bit 1 SBRS1 Bit 0 SBRS0 Bit 7 (CES): Clock Edge Select Bit 0 : Data shift out on rising edge, and shifts in on falling edge. Data is on hold during low-level. 1 : Data shift out falling edge, and shift in on rising edge. Data is on hold during high-level. Bit 6 (SPIE): SPI Enable Bit 0 : Disable SPI mode 1 : Enable SPI mode Bit 5 (SRO): SPI Read Overflow Bit 0 : No overflow 1 : A new data is received while the previous data is still being held in the SPIRB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, user is required to read the SPIRB register although only the transmission is implemented. This can only occur in slave mode. * 27 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bit 4 (SSE): SPI Shift Enable Bit 0 : Reset as soon as the shift is complete, and the next byte is read to shift. 1 : Start to shift, and remain on "1" while the current byte is still being transmitted. Bit 3 (SDOC): SDO Output Status Control Bit 0 : After the serial data output, the SDO remain high. 1 : After the serial data output, the SDO remain low. Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits SBRS2 0 0 0 0 1 1 1 1 SBRS1 0 0 1 1 0 0 1 1 SBRS0 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Master Slave Slave SPI Baud Rate Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 Timer2 /SS enable /SS disable 6.2.36 Bank 2 RE SPIR (SPI Read Buffer) Bit 7 SRB7 Bit 6 SRB6 Bit 5 SRB5 Bit 4 SRB4 Bit 3 SRB3 Bit 2 SRB2 Bit 1 SRB1 Bit 0 SRB0 Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer 6.2.37 Bank 2 RF SPIW (SPI Write Buffer) Bit 7 SWB7 Bit 6 SWB6 Bit 5 SWB5 Bit 4 SWB4 Bit 3 SWB3 Bit 2 SWB2 Bit 1 SWB1 Bit 0 SWB0 Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer 28 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.38 Bank 3 R5 URC (UART Control Register) Bit 7 URTD8 Bit 6 Bit 5 Bit 4 BRATE2 Bit 3 BRATE1 Bit 2 BRATE0 Bit 1 UTBE Bit 0 TXE UMODE1 UMODE0 Bit 7 (URTD8): Transmission Data Bit 8 Bits 6~5 (UMODE1~UMODE0): UART Transmission Mode Select Bit UMODE1 UMODE0 0 0 1 1 0 1 0 1 UART Mode Mode 1 : 7-Bit Mode 2 : 8-Bit Mode 3 : 9-Bit Reserved Bits 4~2 (BRATE2~BRATE0): Transmit Baud Rate Select (Tuart=Fc/16) BRATE2 0 0 0 0 1 1 1 1 BRATE1 0 0 1 1 0 0 1 1 BRATE0 0 1 0 1 0 1 0 1 Baud Rate Tuart/13 Tuart/26 Tuart/52 Tuart/104 Tuart/208 Tuart/416 Timer 1 Reserved e.g. Fc = 8MHz 38400 19200 9600 4800 2400 1200 Bit 1 (UTBE): UART transfer buffer empty flag. Set to 1 when transfer buffer is empty. Reset to 0 automatically when write in to URTD register. UTBE bit will be cleared by hardware when enabling transmission. The UTBE bit is read-only. Therefore, writing to the URTD register is necessary to start transmit shifting. Bit 0 (TXE): Enable transmission 0 : Disable 1 : Enable Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 29 EM78P510N 8-Bit Microcontrollers 6.2.39 Bank 3 R6 URS (UART Status) Bit 7 URRD8 Bit 6 EVEN Bit 5 PRE Bit 4 PRERR Bit 3 OVERR Bit 2 FMERR Bit 1 URBF Bit 0 RXE Bit 7 (URRD8): Receiving Data Bit 8 Bit 6 (EVEN): Select Parity Check 0 : Odd parity 1 : Even parity Bit 5 (PRE): Enable Parity Addition 0 : Disable 1 : Enable Bit 4 (PRERR): Parity Error Flag Set to 1 when parity error occurs and cleared to 0 by software. Bit 3 (OVERR): Over Running Error Flag Set to 1 when overrun error occurs and cleared to 0 by software. Bit 2 (FMERR): Framing Error Flag Set to 1 when framing error occurs and cleared to 0 by software. Bit 1 (URBF): UART Read Buffer Full Flag Set to 1 when one character is received. Reset to 0 automatically when read from URS register. URBF will be cleared by hardware when enabling receiving. And URBF bit is read-only. Therefore, reading the URS register is necessary to avoid overrun error. Bit 0 (RXE): Enable Receiving 0 : Disable 1 : Enable 6.2.40 Bank 3 R7 URRD (UART_RD Data Buffer) Bit 7 URRD7 Bit 6 URRD6 Bit 5 URRD5 Bit 4 URRD4 Bit 3 URRD3 Bit 2 URRD2 Bit 1 URRD1 Bit 0 URRD0 Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only. 30 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.41 Bank 3 R8 URTD (UART_TD Data Buffer) Bit 7 URTD 7 Bit 6 URTD 6 Bit 5 URTD 5 Bit 4 URTD 4 Bit 3 URTD 3 Bit 2 URTD 2 Bit 1 URTD 1 Bit 0 URTD0 Bits 7~0 (URTD7~URTD0): UART Transmit Data Buffer. Write only. 6.2.42 Bank 3 R9 ADCR (A/D Control Register) Bit 7 ADRUN Bit 6 ADP Bit 5 ADCK1 Bit 4 ADCK0 Bit 3 ADIS3 Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0 Bit 7 (ADRUN): AD Conversion Start 0 : Reset on completion of the conversion by hardware, this bit cannot be reset by software. 1 : Conversion starts Bit 6 (ADP): A/D Power Control Bits 5~4 (ADCK1~ADCK0): AD Converted Time Select Bits ADCK1 ADCK0 0 0 1 1 0 1 0 1 Clock Source Fc/4 Fc/16 Fc/32 Fc/64 Max. Operating Frequency (Fc) 1MHz 4MHz 8MHz 16MHz Bits 3~0 (ADIS3~ADIS0): A/D Input Select Bits ADIS3 0 0 0 0 0 0 0 0 1 1 1 1 ADIS2 0 0 0 0 1 1 1 1 0 0 0 0 ADIS1 0 0 1 1 0 0 1 1 0 0 1 1 ADIS0 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Pin AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 31 EM78P510N 8-Bit Microcontrollers 6.2.43 Bank 3 RA ADICH (A/D Input Control Register) Bit 7 CALI Bit 6 ADREF Bit 5 0 Bit 4 0 Bit 3 ADE11 Bit 2 ADE10 Bit 1 ADE9 Bit 0 ADE8 Bit 7 (CALI): Calibration Enable Bit for A/D Offset 0 : disable Calibration 1 : enable Calibration Bit 6 (ADREF): AD Reference Voltage Input Select 0 : Internal VDD, P84 is used as I/O. 1 : External reference pin, P84 is used as reference input pin. Bits 5~4: Reserved Bits 3~0 (ADE11~ADE8): AD Input Pin Enable Control 0 : Functions as I/O pin 1 : Functions as analog input pin 6.2.44 Bank 3 RB ADICL (A/D Input Control Register) Bit 7 ADE7 Bit 6 ADE6 Bit 5 ADE5 Bit 4 ADE4 Bit 3 ADE3 Bit 2 ADE2 Bit 1 ADE1 Bit 0 ADE0 Bits 7~0 (ADE7~ADE0): AD input pin enable control. 0 : Functions as I/O pin 1 : Functions as analog input pin 6.2.45 Bank 3 RC ADDH (AD High 8-bit Data Buffer) Bit 7 ADD11 Bit 6 ADD10 Bit 5 ADD9 Bit 4 ADD8 Bit 3 ADD7 Bit 2 ADD6 Bit 1 ADD5 Bit 0 ADD4 Bits 7~0 (ADD11~ADD4): AD High 8-Bit Data Buffer 6.2.46 Bank 3 RD ADDL (AD Low 4-bit Data Buffer) Bit 7 SIGN Bit 6 VOF[2] Bit 5 VOF[1] Bit 4 VOF[0] Bit 3 ADD3 Bit 2 ADD2 Bit 1 ADD1 Bit 0 ADD0 Bit 7 (SIGN): Polarity Bit of Offset Voltage 0 : Negative voltage 1 : Positive voltage 32 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bits 6~4 (VOF[2]~VOF[0]): Offset Voltage Bits VOF[2] 0 0 0 0 1 1 1 1 VOF[1] 0 0 1 1 0 0 1 1 VOF[0] 0 1 0 1 0 1 0 1 EM78P510N 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB Bits 3~0 (ADD3~ADD0): AD Low 4-Bit Data Buffer 6.2.47 Bank 3 RE EIESH (External Interrupt Edge Select High Byte Control Register) Bit 7 EIES7 Bit 6 EIES6 Bit 5 EIES5 Bit 4 EIES4 Bit 3 EIES3 Bit 2 EIES2 Bit 1 EIES1 Bit 0 EIES0 Bits 7~0 (EIES7~EIES0): External Interrupt 7~0 Edge Select Bit 0 : Falling edge interrupt 1 : Rising edge interrupt 6.2.48 Bank 3 RF EIESL (External Interrupt Edge Select Low Byte Control Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 ADWK Bit 3 INTWK9 Bit 2 INTWK8 Bit 1 EIES9 Bit 0 EIES8 Bits 7~5: Reserved Bit 4 (ADWK): A/D Converter Wake-up Function Enable Bit 0 : Disable 1 : Enable Bits 3~2 (INTWK9~INTWK8): External Interrupt 9~8 Wake-up Function Enable Bit 0 : Disable 1 : Enable Bits 1~0 (EIES9~EIES8): External Interrupt 9~8 Edge Select Bit 0 : Falling edges interrupt 1 : Rising edges interrupt Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 33 EM78P510N 8-Bit Microcontrollers 6.2.49 Bank 4 R5 LEDDCR (LED Drive Control Register) Bit 7 LEDD7 Bit 6 LEDD6 Bit 5 LEDD5 Bit 4 LEDD4 Bit 3 LEDD3 Bit 2 LEDD2 Bit 1 LEDD1 Bit 0 LEDD0 Bits 7~0 (LEDD7~LEDD0): 8-bit LED Drive Control Registers 0 : Port 9 functions as normal I/O 1 : Port 9 functions as LED direct drive I/O 6.2.50 Bank 4 R6 WBCR (Watchdog Timer and Buzzer Control Register) Bit 7 WTCS Bit 6 WTIE Bit 5 WTIF Bit 4 WTSSB1 Bit 3 WTSSB0 Bit 2 BUZE Bit 1 BSSB1 Bit 0 BSSB0 Bit 7 (WTCS): Watchdog Timer and Buzzer Clock Source Select Bit 0 : Main Clock divided by 256 1 : Sub clock Bit 6 (WTIE): Watch Timer Enable Bit and Interrupt Mask 0 : Disable 1 : Enable Bit 5 (WTIF): Watch Timer Interrupt Flag Bits 4~3 (WTSSB1~ WTSSB0): Watch Timer Interval Select Bits WTSSB1 0 0 1 1 WTSSB0 0 1 0 1 Watch Timer Interval Select (WTCS=1) 1.0S 0.5S 0.25S 3.91ms Bit 2 (BUZE): Buzzer Enable and PORT 91 as Buzzer Output Pin 0 : No action 1 : Enable buzzer output Bits 1~0 (BSSB1~BSSB0): Buzzer Output Frequency Select Bits BSSB1 0 0 1 1 BSSB0 0 1 0 1 Buzzer Signal Select (WTCS=1) 0.5kHz 1kHz 2kHz 4kHz 34 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.51 Bank 4 R7 PIOCR (Port 7 I/O Control Register) Bit 7 IOC77 Bit 6 IOC76 Bit 5 IOC75 Bit 4 IOC74 Bit 3 IOC73 Bit 2 IOC72 Bit 1 IOC71 Bit 0 IOC70 Bits 7~0 (IOC77~IOC70): Port 7 8-Bit I/O Direction Control Registers 0 : Define Port 7 as output port 1 : Define Port 7 as input port 6.2.52 Bank 4 R8 PIOCR (Port 8 I/O Control Register) Bit 7 IOC87 Bit 6 IOC86 Bit 5 IOC85 Bit 4 IOC84 Bit 3 IOC83 Bit 2 IOC82 Bit 1 IOC81 Bit 0 0 Bits 7~1 (IOC87~IOC81): Port 8 7-Bit I/O Direction Control Registers 0 : Define Port 8 as output port 1 : Define Port 8 as input port Bit 0: Reserved 6.2.53 Bank 4 R9 PIOCR (Port 9 I/O Control Register) Bit 7 IOC97 Bit 6 IOC96 Bit 5 IOC95 Bit 4 IOC94 Bit 3 IOC93 Bit 2 IOC92 Bit 1 IOC91 Bit 0 IOC90 Bits 7~0 (IOC97~IOC90): Port 9 8-Bit I/O Direction Control Registers 0 : Define Port 9 as output port 1 : Define Port 9 as input port 6.2.54 Bank 4 RA PIOCR (Port A I/O Control Register) Bit 7 IOCA7 Bit 6 IOCA6 Bit 5 IOCA5 Bit 4 IOCA4 Bit 3 IOCA3 Bit 2 IOCA2 Bit 1 IOCA1 Bit 0 IOCA0 Bits 7~0 (IOCA7~IOCA0): Port A 8-Bit I/O Direction Control Registers 0 : Define Port A as output port 1 : Define Port A as input port Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 35 EM78P510N 8-Bit Microcontrollers 6.2.55 Bank 4 RB PIOCR(Port B I/O Control Register) Bit 7 IOCB7 Bit 6 IOCB6 Bit 5 IOCB5 Bit 4 IOCB4 Bit 3 IOCB3 Bit 2 IOCB2 Bit 1 IOCB1 Bit 0 IOCB0 Bits 7~0 (IOCB7~IOCB0): Port B 8-Bit I/O Direction Control Registers 0 : Define Port B as output port 1 : Define Port B as input port 6.2.56 Bank 4 RC PIOCR (Port C I/O Control Register) Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 IOCC3 Bit 2 IOCC2 Bit 1 IOCC1 Bit 0 IOCC0 Bits 7~4: Reserved Bits 3~0 (IOCC3~IOCC0): Port C 4-Bit I/O Direction Control Registers 0 : Define Port C as output port 1 : Define Port C as input port 6.2.57 Bank 4 RF WKCR (Wake-up Control Register) Bit 7 INTWK7 Bit 6 INTWK6 Bit 5 INTWK5 Bit 4 INTWK4 Bit 3 INTWK3 Bit 2 INTWK2 Bit 1 INTWK1 Bit 0 INTWK0 Bits 7~0 (INTWK7~INTWK0): External Interrupt 7~0 Wake Up Function Enable Bit 0 : Disable 1 : Enable 6.2.58 Bank 5 R6 UARC2 (UART Control Register 2) Bit 7 0 Bit 6 0 Bit 5 UARTE Bit 4 0 Bit 3 UINVEN Bit 2 0 Bit 1 0 Bit 0 0 Bits 7~6: Reserved Bit 5 (UARTE): UART Function Enable 0 : UART functions disable. PB4, PB5 as general I/O 1 : UART functions enable. PB4, PB5 as UART Rx, Tx pin Bit 4: Reserved Bit 3 (UINVEN): Enable UART TX and Rx Port Inverse Output 0 : Disable Tx and Rx port inverse output 1 : Enable Tx and Rx port inverse output Bits 2~0: Reserved 36 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.59 Bank 5 R7 P7PHCR (Port 7 Pull High Control Register) Bit 7 PH77 Bit 6 PH76 Bit 5 PH75 Bit 4 PH74 Bit 3 PH73 Bit 2 PH72 Bit 1 PH71 Bit 0 PH70 Bits 7~0 (PH77~PH70): Port 7 8-Bit I/O Pull High Control Registers 0 : Pull high disable 1 : Pull high enable 6.2.60 Bank 5 R8 P8PHCR (Port 8 Pull High Control Register) Bit 7 PH87 Bit 6 PH86 Bit 5 PH85 Bit 4 PH84 Bit 3 PH83 Bit 2 PH82 Bit 1 PH81 Bit 0 0 Bits 7~1 (PH87~PH81): PORT 8 7-Bit I/O Pull High Control Registers 0 : Pull high disable 1 : Pull high enable Bit 0: Reserved 6.2.61 Bank 5 R9 P9PHCR (Port 9 Pull-high Control Register) Bit 7 PH97 Bit 6 PH96 Bit 5 PH95 Bit 4 PH94 Bit 3 PH93 Bit 2 PH92 Bit 1 PH91 Bit 0 PH90 Bits 7~0 (PH97~PH90): Port 9 8-bit I/O Pull-high Control Registers 0 : Pull-high disable 1 : Pull-high enable 6.2.62 Bank 5 RA PAPHCR (Port A Pull-high Control Register) Bit 7 PHA7 Bit 6 PHA6 Bit 5 PHA5 Bit 4 PHA4 Bit 3 PHA3 Bit 2 PHA2 Bit 1 PHA1 Bit 0 PHA0 Bits 7~0 (PHA7~PHA0): Port A 8-bit I/O Pull-high Control Registers 0 : Pull-high disable 1 : Pull-high enable Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 37 EM78P510N 8-Bit Microcontrollers 6.2.63 Bank 5 RB PBPHCR (Port B Pull-high Control Register) Bit 7 PHB7 Bit 6 PHB6 Bit 5 PHB5 Bit 4 PHB4 Bit 3 PHB3 Bit 2 PHB2 Bit 1 PHB1 Bit 0 PHB0 Bits 7~0 (PHB7~PHB0): Port B 8-Bit I/O Pull-high Control Registers 0 : Pull high disable 1 : Pull high enable 6.2.64 Bank 5 RC PCPHCR (Port C Pull High Control Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 PHC3 Bit 2 PHC2 Bit 1 PHC1 Bit 0 PHC0 Bits 7~4: Reserved Bits 3~0 (PHC3~PHC0): Port C 4-Bit I/O Pull-high Control Registers 0 : Pull high disable 1 : Pull high enable 6.2.65 Bank 6 R6 LVRCR (Low Voltage Reset Control Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 LVREN Bit 1 LVRS1 Bit 0 LVRS0 R6 use only ICE510 simulator Bits 7~3: Reserved Bit 2 (LVREN): Low Voltage Reset Enable Bit 0 : Disable 1 : Enable Bits 1~0 (LVRS1~LVRS0): Low Voltage Reset Voltage Select Bits LVRS1 0 0 1 LVRS0 0 1 0 Reset Voltage 2.6V 3.3V 3.9V 6.2.66 Bank 6 R7 P7ODCR (Port 7 Open Drain Control Register) Bit 7 OD77 Bit 6 OD76 Bit 5 OD75 Bit 4 OD74 Bit 3 OD73 Bit 2 OD72 Bit 1 OD71 Bit 0 OD70 Bits 7~0 (OD77~OD70): Port 7 8-Bit I/O Open Drain Control Registers 0 : Open drain disable 1 : Open drain enable 38 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.2.67 Bank 6 R8 P8ODCR (Port 8 Open Drain Control Register) Bit 7 OD87 Bit 6 OD86 Bit 5 OD85 Bit 4 OD84 Bit 3 OD83 Bit 2 OD82 Bit 1 OD81 Bit 0 0 Bits 7~1 (OD87~OD80): Port 8 7-bit I/O Open Drain Control Registers 0 : Open drain disable 1 : Open drain enable Bit 0: Reserved 6.2.68 Bank 6 R9 P9ODCR (Port 9 Open Drain Control Register) Bit 7 OD97 Bit 6 OD96 Bit 5 OD95 Bit 4 OD94 Bit 3 OD93 Bit 2 OD92 Bit 1 OD91 Bit 0 OD90 Bits 7~0 (OD97~OD90): Port 9 8-Bit I/O Open Drain Control Registers 0 : Open drain disable 1 : Open drain enable 6.2.69 Bank 6 RA PAODCR (Port A Open Drain Control Register) Bit 7 ODA7 Bit 6 ODA6 Bit 5 ODA5 Bit 4 ODA4 Bit 3 ODA3 Bit 2 ODA2 Bit 1 ODA1 Bit 0 ODA0 Bits 7~0 (ODA7~ODA0): Port A 8-Bit I/O Open Drain Control Registers 0 : Open drain disable 1 : Open drain enable 6.2.70 Bank 6 RB PBODCR (Port B Open Drain Control Register) Bit 7 ODB7 Bit 6 ODB6 Bit 5 ODB5 Bit 4 ODB4 Bit 3 ODB3 Bit 2 ODB2 Bit 1 ODB1 Bit 0 ODB0 Bits 7~0 (ODB7~ODB0): Port B 8-Bit I/O Open Drain Control Registers 0 : Open drain disable 1 : Open drain enable 6.2.71 Bank 6 RC (Port C) Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Bits 7~4: Reserved Bits 3~0 (RC3~RC0): Port C 4-Bit I/O Registers 6.2.72 R10~R3F (General Purpose Register) R10~R1F and R20~R3F (Banks 0~7) are general purpose registers. Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 39 EM78P510N 8-Bit Microcontrollers 6.3 TCC/WDT Pre-scaler Registers for the TCC/WDT Circuit R_BANK Address NAME Bank 0 0X0D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWTCR WDTE WPSR2 WPSR1 WPSR0 TCCS R/W R/W R/W R/W R/W TPSR2 TPSR1 TPSR0 R/W R/W R/W Bank 0 0x0E IMR T1IE R/W LVDIE R/W ADIE R/W SPIE URTIE EXIE9 EXIE8 R/W R/W R/W R/W TCIE R/W Bank 0 0x0F ISR T1IF R/W LVDIF R/W ADIF R/W SPIIF URTIF EXIF9 EXIF8 R/W R/W R/W R/W TCIF R/W There are two 8-bit counters available as prescalers for the TCC and WDT, respectively. The TPSR0~TPSR2 bits of the Bank 0 RD (TWTCR) register are used to determine the ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the Bank 0 RD (TWTCR) register are used to determine the WDT prescaler. The prescaler (TPSR0~TPSR2) will be cleared by the instructions each time they are written into TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. Fig.6-4 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock main clock or sub clock (32.768kHz). If TCC signal source is from the internal clock, TCC will be incremented by 1 at every instruction cycle (without prescaler). As illustrated in Fig. 6-4. The watchdog timer is a free running on-chip RC oscillator. The WDT will continue running even after the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode by software programming. Refer to WDTE bit of Bank 0 RD (TWTCR) register. With no prescaler, the WDT time-out period is approximately 18 ms1. 1 Note: VDD=5V, Setup time period = 16.5ms 30% VDD=3V, Setup time period = 18ms 30% Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) 40 * EM78P510N 8-Bit Microcontrollers Figure 6-4 TCC/WDT Block Diagram 6.4 I/O Port Registers for I/O Circuit R_BANK Bank 4 Address Name Bit 7 IOC7 R/W Bit 6 IOC6 R/W Bit 5 IOC5 R/W Bit 4 IOC4 R/W Bit 3 IOC3 R/W Bit 2 IOC2 R/W Bit 1 IOC1 R/W Bit 0 IOC0 R/W 0X07~0X0C PIOCR Bank 5 0X07~0X0C PHCR PH7 R/W PH6 R/W PH5 R/W PH4 R/W PH3 R/W PH2 R/W PH1 R/W PH0 R/W Bank 6 0X07~0X0B ODCR OD7 R/W OD6 R/W OD5 R/W OD4 R/W OD3 R/W OD2 R/W OD1 R/W OD0 R/W The I/O registers, (Port 7, Port 8, Port 9, Port A, Port B and Port C), are bidirectional tri-state I/O ports. All pins are pulled-high internally by software. Likewise, Port 7, Port 8, Port 9, Port A, Port B and Port C, can have open-drain output also through software. Port 7 [7:4], Port B [3:0] and Port 8 [3:2] provides an input status changed interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register Bank 4 R7 ~ RC. The I/O registers and I/O control registers are both readable and writeable. The I/O interface circuits are shown in Fig. 6-5. The I/O cannot be set to pull-high and output low at the same time. It can relatively increase the power consumption. Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 41 EM78P510N 8-Bit Microcontrollers Note: Open-drain is not shown in the figure. Figure 6-5 Circuits of I/O Port and I/O Control Register for Ports 7~ 9, and Ports A ~ C 6.5 Reset and Wake-up A Reset can be caused by: Power-on reset WDT timeout (if enabled) LVR Reset RESET pin pulls low NOTE The power-on reset circuit is always enabled, it will reset the CPU at 2.3V and power consumption is 0.5A. Once a Reset occurs, the following functions are performed: The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The TCC/Watchdog timer and prescaler are cleared. When power is on, all bits of R5 and R6 are cleared. The other registers are described in Table 2 42 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Table 2 Summary of the Registers Initialized Values Address Name Reset Type Bit Name 0x00 R0 (IAR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x01 R1 (TCC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x02 R2 (PC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x03 R3 (SR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x04 R4 (RSR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x05 R5 (RBSR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x06 R6 (RPSR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x07 R7 (Port 7) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x08 R8 (Port 8) Power-on /RESET and WDT Wake-up from Pin Change Bit 7 U P P 0 0 P 0 0 Bit 6 U P P 0 0 P 0 0 Bit 5 U P P 0 0 P 0 0 Bit 4 U P P 0 0 P 0 0 Bit 3 U P P 0 0 P 0 0 Bit 2 U P P 0 0 P 0 0 Bit 1 U P P 0 0 P 0 0 Bit 0 U P P 0 0 P 0 0 Continue to execute next instruction LVDEN LVDS1 LVDS0 0 0 P VDB 1 1 P 0 0 0 P 0 0 0 P R77 1 1 P R87 1 1 P 0 0 P BNC 1 1 P 0 0 0 P 0 0 0 P R76 1 1 P R86 1 1 P 0 0 P X U P P 0 0 0 P 0 0 0 P R75 1 1 P R85 1 1 P T 1 t t X U P P 0 0 0 P 0 0 0 P R74 1 1 P R84 1 1 P P 1 t t X U P P 0 0 0 P 0 0 0 P R73 1 1 P R83 1 1 P Z U P P X U P P BS2 0 0 P PS2 0 0 P R62 1 1 P R82 1 1 P DC U P P X U P P BS1 0 0 P PS1 0 0 P R71 1 1 P R81 1 1 P C U P P X U P P BS0 0 0 P PS0 0 0 P R70 1 1 P 0 0 0 P Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 43 EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 R97 1 1 P RA7 1 1 P RB7 1 1 P 0 0 0 P Bit 6 R96 1 1 P RA6 1 1 P RB6 1 1 P CLK2 0 0 P Bit 5 R95 1 1 P RA5 1 1 P RB5 1 1 P CKL1 0 0 P Bit 4 R94 1 1 P RA4 1 1 P RB4 1 1 P CLK0 0 0 P Bit 3 R93 1 1 P RA3 1 1 P RB3 1 1 P IDLE 1 1 P Bit 2 R92 1 1 P RA2 1 1 P RB2 1 1 P 0 0 0 P Bit 1 R91 1 1 P RA1 1 1 P RB1 1 1 P 0 0 0 P Bit 0 R90 1 1 P RA0 1 1 P RB0 1 1 P CPUS 1 1 P 0x09 R9 (Port 9) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0A RA (Port A) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0B RB (Port B) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0C RC (SCCR) Power-on /RESET and WDT Wake-Up from Pin Change Bit Name WDTE WPSR2 WPSR1 WPSR0 TCCS 0 0 P T1IE 0 0 P T1IF 0 0 P 0 0 P LVDIE 0 0 P LVDIF 0 0 P 0 0 P ADIE 0 0 P ADIF 0 0 P BS1 0 0 P 0 0 0 P 0 0 P SPIE 0 0 P SPIIF 0 0 P BS0 0 0 P 0 0 P URTIE 0 0 P URTIF 0 0 P DS1 0 0 P TPSR2 TPSR1 TPSR0 0 0 P EXIE9 0 0 P EXIF9 0 0 P DS0 0 0 P 0 0 P EXIE8 0 0 P EXIF8 0 0 P 0 0 P TCIE 0 0 P TCIF 0 0 P 0x0D RD (TWTCR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0E RE (IMR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0F RF (ISR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name LCDEN LCDPYTE 0 0 P 0 0 0 P 0 0 P 0 0 0 P LCDF1 LCDF0 0 0 P 0 0 P Bank1 0x05 Bank 1 R5 (LCDCR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0 0X06 R6 (LCDAR) Power-on /RESET and WDT Wake-up from Pin Change 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 44 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 0 0 P 0 0 0 P 0 0 P 0 0 0 P 0 0 P 0 0 0 P COM5 0 0 P SEG5 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0X07 R7 (LCDBR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name LCDC1 LCDC0 LCDVC2 LCDVC1 LCDVC0 1 1 P COM4 0 0 P SEG4 0 0 P 1 1 P COM3 0 0 P SEG3 0 0 P 1 1 P COM2 0 0 P SEG2 0 0 P 1 1 P COM1 0 0 P SEG1 0 0 P SEG9 0 0 P 1 1 P COM0 0 0 P SEG0 0 0 P SEG8 0 0 P 0X08 R8 Power-on (LCDVCR) /RESET and WDT Wake-up from Pin Change Bit Name COM7 COM6 0 0 P SEG7 0 0 P 0 0 P SEG6 0 0 P 0X09 R9 Power-on (LCDCCR) /RESET and WDT Wake-up from Pin Change Bit Name 0X0A RA Power-on (LCDSCR0) /RESET and WDT Wake-up from Pin Change Bit Name SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 0 0 P 0 0 0 P EXIE7 0 0 P EXIF7 0 0 P TIS1 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0X0B RB Power-on (LCDSCR1) /RESET and WDT Wake-up from Pin Change Bit Name SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 0 0 P EXIE6 0 0 P EXIF6 0 0 P TIS0 0 0 P 0 0 P EXIE5 0 0 P EXIF5 0 0 P 0 0 P EXIE4 0 0 P EXIF4 0 0 P 0 0 P EXIE3 0 0 P EXIF3 0 0 P 0 0 P EXIE2 0 0 P EXIF2 0 0 P T1P2 0 0 P 0 0 P EXIE1 0 0 P EXIF1 0 0 P T1P1 0 0 P 0 0 P EXIE0 0 0 P EXIF0 0 0 P T1P0 0 0 P 0X0C RC Power-on (LCDSCR2) /RESET and WDT Wake-up from Pin Change Bit Name 0X0E RE (EIMR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0X0F RF (EISR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name T1MS2 T1MS1 TIMS0 0 0 P 0 0 P 0 0 P Bank 2 0X05 Bank2 R5 (T1CR) Power-on /RESET and WDT Wake-up from Pin Change Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 45 EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 T1EN 0 0 P Bit 1 Bit 0 T1MOD TCRB T1CSS1 T1CSS0 T2CSS 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P T1OMS T1OC 0 0 P 0 0 P 0X06 R6 (TSR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0] 0 0 P 0 0 P 0 0 P TD1[5] 0 0 P T2EN 0 0 P 0 0 P TD1[4] 0 0 P 0 0 P TD1[3] 0 0 P 0 0 P TD1[2] 0 0 P T2P2 0 0 P 0 0 P 0 0 P 0X07 R7 (T1PD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name TD1[7] TD1[6] 0 0 P T2IF 0 0 P 0 0 P T2IE 0 0 P TD1[1] TD1[0] 0 0 P T2P1 0 0 P 0 0 P T2P0 0 0 P 0x08 R8 (T1TD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name T2MS1 T2MS0 0 0 P 0 0 P 0X09 R9 (T2CR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] 0 0 P 0 0 P 0 0 P TD2[5] 0 0 P TD0 0 0 P SRO 0 0 P SRB5 U U P 0 0 P TD2[4] 0 0 P 0 0 0 P SSE 0 0 P SRB4 U U P 0 0 P TD2[3] 0 0 P OD3 0 0 P 0 0 P TD2[2] 0 0 P OD4 0 0 P 0 0 P 0 0 P 0X0A RA (T2PD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name TD2[7] TD2[6] 0 0 P DORD 0 0 P CES 0 0 P SRB7 U U P 0 0 P TD1 0 0 P SPIE 0 0 P SRB6 U U P TD2[1] TD2[0] 0 0 P 0 0 0 P 0 0 P RBF 0 0 P 0X0B RB (T2TD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0X0C RC (SPIS) Power-on /RESET and WDT Wake-up from Pin Change Bit Name SDOC SBRS2 SBRS1 SBRS0 0 0 P SRB3 U U P 0 0 P SRB2 U U P 0 0 P SRB1 U U P 0 0 P SRB0 U U P 0X0D RD (SPIC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0X0E RE (SPIR) Power-on /RESET and WDT Wake-up from Pin Change 46 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 SWB7 U U P Bit 6 SWB6 U U P Bit 5 SWB5 U U P Bit 4 SWB4 U U P Bit 3 SWB3 U U P Bit 2 SWB2 U U P Bit 1 SWB1 U U P Bit 0 SWB0 U U P TXE 0 0 P RXE 0 0 P 0X0F RF (SPIW) Power-on /RESET and WDT Wake-up from Pin Change Bit Name URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE U P P URRD 8 U P P 0 0 P EVEN 0 0 P 0 0 P PRE 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P Bank3 0x05 Bank3 R5 (URC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name PRERR OVERR FMERR URBF 0 0 P 0 0 P 0 0 P 0 0 P 0x06 R6 (URS) Power-on /RESET and WDT Wake-up from Pin Change Bit Name URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0 0 P P 0 P P 0 P P 0 P P 0 P P 0 P P 0 P P 0 P P 0x07 R7 (URRD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0 0 P P ADRUN 0 0 P CALI 0 0 P ADE7 0 0 P 0 P P ADP 0 0 P ADREF 0 0 P ADE6 0 0 P 0 P P 0 P P 0 P P 0 P P ADIS2 0 0 P 0 P P ADIS1 0 0 P ADE9 0 0 P ADE1 0 0 P ADD5 0 0 P 0 P P ADIS0 0 0 P ADE8 0 0 P ADE0 0 0 P ADD4 0 0 P 0x08 R8 (URTD) Power-on /RESET and WDT Wake-up from Pin Change Bit Name ADCK1 ADCK0 ADIS3 0 0 P 0 0 0 P ADE5 0 0 P ADD9 0 0 P 0 0 P 0 0 0 P ADE4 0 0 P ADD8 0 0 P 0 0 P 0x09 R9 (ADCR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name ADE11 ADE10 0 0 P ADE3 0 0 P ADD7 0 0 P 0 0 P ADE2 0 0 P ADD6 0 0 P 0x0A RA (ADICH) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0B RB (ADICL) Power-on /RESET and WDT Wake-up from Pin Change Bit Name ADD11 ADD10 0 0 P 0 0 P 0x0C RC (ADDH) Power-on /RESET and WDT Wake-up from Pin Change Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 47 EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 SIGN 0 0 P EIES7 0 0 P 0 0 0 P Bit 6 Bit 5 Bit 4 Bit 3 ADD3 0 0 P EIES3 0 0 P Bit 2 ADD2 0 0 P EIES2 0 0 P Bit 1 ADD1 0 0 P EIES1 0 0 P Bit 0 ADD0 0 0 P EIES0 0 0 P EIES8 0 0 P VOF[2] VOF[1] VOF[0] 0 0 P EIES6 0 0 P 0 0 0 P 0 0 P EIES5 0 0 P 0 0 0 P 0 0 P EIES4 0 0 P 0x0D RD (ADDL) Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x0E RE (EIESH) Power-on /RESET and WDT Wake-up from Pin Change Bit Name ADWK INTWK9 INTWK8 EIES9 0 0 P 0 0 P 0 0 P 0 0 P 0x0F RF (EIESL) Power-on /RESET and WDT Wake-up from Pin Change Bank4 0x05 Bank4 R5 (LEDDCR) Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name LEDD7 LEDD6 LEDD5 LEDD4 LEDD3 LEDD2 LEDD1 LEDD0 0 0 P WTCS 0 0 P 0 0 P WTIE 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P 0 0 P WTIF WTSSB1 WTSSB0 BUZE 0 0 P IOC75 1 1 P IOC85 1 1 P IOC95 1 1 P IOCA5 1 1 P 0 0 P IOC74 1 1 P IOC84 1 1 P IOC94 1 1 P IOCA4 1 1 P 0 0 P IOC73 1 1 P IOC83 1 1 P IOC93 1 1 P IOCA3 1 1 P 0 0 P IOC72 1 1 P IOC82 1 1 P IOC92 1 1 P IOCA2 1 1 P BSSB1 BSSB0 0 0 P IOC71 1 1 P IOC81 1 1 P IOC91 1 1 P 0 0 P IOC70 1 1 P 0 0 0 P IOC90 1 1 P 0x06 R6 (WBCR) Power-on /RESET and WDT Wake-up from Pin Change Bit Name IOC77 IOC76 1 1 P 1 1 P 0x07 R7 (IOC7) Power-on /RESET and WDT Wake-up from Pin Change Bit Name IOC87 IOC86 1 1 P 1 1 P 0x08 R8 (IOC8) Power-on /RESET and WDT Wake-up from Pin Change Bit Name IOC97 IOC96 1 1 P 1 1 P 0x09 R9 (IOC9) Power-on /RESET and WDT Wake-up from Pin Change Bit Name IOCA7 IOCA6 1 1 P 1 1 P IOCA1 IOCA0 1 1 P 1 1 P 0x0A RA (IOCA) Power-on /RESET and WDT Wake-up from Pin Change 48 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 Bit 6 Bit 5 IOCB5 1 1 P 1 1 1 P Bit 4 IOCB4 1 1 P 1 1 1 P Bit 3 IOCB3 1 1 P IOCC3 1 1 P Bit 2 IOCB2 1 1 P IOCC2 1 1 P Bit 1 Bit 0 IOCB7 IOCB6 1 1 P 1 1 1 P 1 1 P 1 1 1 P IOCB1 IOCB0 1 1 P 1 1 P 0x0B RB (IOCB) Power-on /RESET and WDT Wake-up from Pin Change Bit Name IOCC1 IOCC0 1 1 P 1 1 P 0x0C RC (IOCC) Power-on /RESET and WDT Wake-up from Pin Change Bit Name INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2 INTWK1 INTWK0 0 0 P 0 0 0 P PH77 0 0 P PH87 0 0 P PH97 0 0 P PHA7 0 0 P PHB7 0 0 P 0 0 P 0 0 0 P PH76 0 0 P PH86 0 0 P PH96 0 0 P PHA6 0 0 P PHB6 0 0 P 0 0 P UARTE 0 0 P PH75 0 0 P PH85 0 0 P PH95 0 0 P PHA5 0 0 P PHB5 0 0 P 0 0 P 0 0 0 P PH74 0 0 P PH84 0 0 P PH94 0 0 P PHA4 0 0 P PHB4 0 0 P 0 0 P UINVEN 0X0F RF (WKCR) Power-on /RESET and WDT Wake-up from Pin Change 0 0 P 0 0 0 P PH72 0 0 P PH82 0 0 P PH92 0 0 P PHA2 0 0 P PHB2 0 0 P 0 0 P 0 0 0 P PH71 0 0 P PH81 0 0 P PH91 0 0 P PHA1 0 0 P PHB1 0 0 P 0 0 P 0 0 0 P PH70 0 0 P 0 0 0 P PH90 0 0 P PHA0 0 0 P PHB0 0 0 P Bank5 0x06 Bank5 R6 (UARC2) Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0 0 P PH73 0 0 P PH83 0 0 P PH93 0 0 P PHA3 0 0 P PHB3 0 0 P 0x07 R7 Power-on (P7PHCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x08 R8 Power-on (P8PHCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x09 R9 Power-on (P9PHCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x0A RA Power-on (PAPHCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x0B RB Power-on (PBPHCR) /RESET and WDT Wake-up from Pin Change Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 49 EM78P510N 8-Bit Microcontrollers Address Name Reset Type Bit Name Bit 7 0 0 0 P OD77 0 0 P OD87 0 0 P OD97 0 0 P ODA7 0 0 P ODB7 0 0 P 1 1 1 P U U P Bit 6 0 0 0 P OD76 0 0 P OD86 0 0 P OD96 0 0 P ODA6 0 0 P ODB6 0 0 P 1 1 1 P U U P Bit 5 0 0 0 P OD75 0 0 P OD85 0 0 P OD95 0 0 P ODA5 0 0 P ODB5 0 0 P 1 1 1 P U U P Bit 4 0 0 0 P OD74 0 0 P OD84 0 0 P OD94 0 0 P ODA4 0 0 P ODB4 0 0 P 1 1 1 P U U P Bit 3 PHC3 0 0 P OD73 0 0 P OD83 0 0 P OD93 0 0 P ODA3 0 0 P ODB3 0 0 P RC3 1 1 P U U P Bit 2 PHC2 0 0 P OD72 0 0 P OD82 0 0 P OD92 0 0 P ODA2 0 0 P ODB2 0 0 P RC2 1 1 P U U P Bit 1 PHC1 0 0 P OD71 0 0 P OD81 0 0 P OD91 0 0 P ODA1 0 0 P ODB1 0 0 P RC1 1 1 P U U P Bit 0 PHC0 0 0 P OD70 0 0 P 0 0 0 P OD90 0 0 P ODA0 0 0 P ODB0 0 0 P RC0 1 1 P U U P 0x0C RC Power-on (PCPHCR) /RESET and WDT Wake-up from Pin Change Bank6 R7 (P7ODCR) Bit Name Power-on /RESET and WDT Wake-up from Pin Change Bit Name 0x08 R8 Power-on (P8ODCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x09 R9 Power-on (P9ODCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x0A RA Power-on (PAODCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x0B RB Power-on (PBODCR) /RESET and WDT Wake-up from Pin Change Bit Name 0x0C RC Power-on /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x10~ R10~R3F 0x3F /RESET and WDT Wake-up from Pin Change Legend: "x" = not used "u" = unknown or don't care Bank6 0x07 "P" = previous value before reset 50 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers The controller can be awakened from sleep mode and idle mode. The wake-up signals list as following. Wake-up Signal TCC time out Sleep Mode x Wake-up + interrupt (if enabled) + next instruction x Idle Mode Wake-up + interrupt + next instruction Wake-up + interrupt(if enabled) + next instruction Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction x Wake-up + interrupt + next instruction Wake-up + interrupt(if interrupt enable) + next instruction Wake-up + interrupt + next instruction RESET Green Mode Normal Mode Interrupt Interrupt INT pin Interrupt Interrupt Timer 1 Interrupt Interrupt Timer 2 x Interrupt Interrupt UART SPI LVD x x x Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt A/D Wake-up + interrupt(if enabled) + next instruction Interrupt Interrupt Watch timer WDT time out x RESET Interrupt RESET Interrupt RESET Note: User must set the wake-up register (Bank 3 RF(EIESL) Bits 2~4 and Bank 4 RF(WKCR) Bits 0~7). Wake up from INT pin or A/D in sleep and idle mode After wake up: 1. If interrupt is enabled interrupt+ next instruction 2. If interrupt is disabled next instruction Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 51 EM78P510N 8-Bit Microcontrollers 6.6 Oscillator 6.6.1 Oscillator Modes The EM78P510N can be operated in the three different oscillator modes for the main oscillator (R-OSCI, OSCO), namely, RC oscillator with external resistor and Internal capacitor mode (IC), crystal oscillator mode, and PLL operation mode. User can select one of those three modes by programming FMMD1 and FMMD0 in the Code Option register, the sub-oscillator can be operated in crystal mode and ERIC mode. Table 3 shows these three modes are defined. Table 3 Oscillator Modes Defined by FSMD, FMMD1, FMMD0. FSMD 0 0 0 0 1 1 1 1 FMMD1 0 0 1 1 0 0 1 1 FMMD0 0 1 0 1 0 1 0 1 Main Clock RC type (ERIC) Crystal type PLL type PLL type RC type (ERIC) Crystal type PLL type Crystal Sub-clock RC type (ERIC) RC type (ERIC) RC type (ERIC) RC type (ERIC) Crystal type Crystal type Crystal type None Table 4 Summary of Maximum Operating Speeds Conditions VDD 2.0 Two clocks 3.0 5.0 Fxt max.(MHz) 4 8 16 6.6.2 Crystal Oscillator/Ceramic Resonators (Crystal) EM78P510N can be driven by an external clock signal through the OSCO pin as shown in Fig.6-6 below. Figure 6-6 External Clock Input Circuit 52 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers In most applications, pin R-OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-7 depicts such circuitry. Table 5 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode. Fig. 6-7 Circuit for Crystal/Resonator Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators Oscillator Source Oscillator Type Frequency 455kHz Ceramic Resonators 2.0 MHz 4.0 MHz Main oscillator Crystal Oscillator 455kHz 1.0MHz 2.0MHz 4.0MHz Sub-oscillator Crystal Oscillator 32.768kHz C1 (pF) 100~150 20~40 10~30 20~40 15~30 15 15 25 C2 (pF) 100~150 20~40 10~30 20~150 15~30 15 15 25 330 C 7404 7404 330 OSCI 7404 Crystal Fig. 6-8 Circuit for Crystal/Resonator-Series Mode Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 53 EM78P510N 8-Bit Microcontrollers Fig. 6-9 Circuit for Crystal/Resonator-Parallel Mode 6.6.3 RC Oscillator Mode with Internal Capacitor If both precision and cost are taken into consideration, the EM78P510N also offers a special oscillation mode, which has a built-in internal capacitor and an external resistor connected to Vcc. The internal capacitor functions as temperature compensator. In order to obtain more accurate frequency, a precise resistor is recommended. Vcc Rext OSCI or Xin Fig. 6-10 Circuit for Internal C Oscillator Mode 54 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Table 6 R Oscillator Frequencies Pin Rext 51k R-OSCI 100k 300k Xin Note: 1 2 Average Fosc 5V, 25C 2.2221 MHz 1.1345 MHz 381.36kHz 32.768kHz Average Fosc 3V, 25C 2.1972 MHz 1.1203 MHz 374.77kHz 32.768kHz 2.2M : Measured based on DIP packages. : The values are for design reference only. 6.6.4 Phase Lock Loop (PLL Mode) When operating in PLL mode, the High frequency is determined by the sub-oscillator. RC (Bank 0) register can be chosen to change to high oscillator frequency. The relation between high frequency (Fm) and sub-oscillator is shown on the table below: Fig. 6-11 Circuit for PLL mode Bits 4~6 (CLK0~CLK2) of RC (Bank 0): Main Clock Selection Bits for PLL Mode (Code Option Select) CLK2 0 0 0 0 1 1 1 CLK1 0 0 1 1 0 0 1 CLK0 0 1 0 1 0 1 X Main Clock Fs x 122 Fs x 61 Fs x 61/2 Fs x 61/4 Fs x 244 Fs x 366 Fs x 488 Example Fs = 32.768K 3.997 MHz 1.998 MHz 0.999 MHz 499.7 kHz 7.995 MHz 11.99 MHz 15.99 MHz Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 55 EM78P510N 8-Bit Microcontrollers 6.7 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. The EM78P510N has a built-in Power-on Reset (POR) with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external reset circuit. It will work well if Vdd rises quickly enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems. 6.7.1 External Power-on Reset Circuit The circuit shown in Fig.6-12 implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough to allow Vdd to reach minimum operation voltage. This circuit is used when the power supply has a slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40K. In this way, the voltage at Pin /RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET. VDD /RESET R D Rin C Fig. 6-12 External Power-on Reset Circuit 56 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.7.2 Residue-Voltage Protection When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig.6-13 and Fig.6-14 show how to build a residue-voltage protection circuit. VDD 33K Q1 /RESET 100K 1N4684 10K VDD Fig. 6-13 Residue Voltage Protection Circuit 1 Fig. 6-14 Residue Voltage Protection Circuit 2 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 57 EM78P510N 8-Bit Microcontrollers 6.8 Interrupt Registers for Interrupt R_BANK Address Bank 0 0x0E Name IMR Bit 7 T1IE R/W Bit 6 R/W Bit 5 R/W Bit 4 SPIE R/W Bit 3 R/W Bit 2 R/W Bit 1 R/W Bit 0 R/W LVDIE ADIE LVDIF ADIF R/W R/W URTIE EXIE9 EXIE8 TCIE URTIF EXIF9 EXIF8 R/W R/W R/W Bank 0 0x0F ISR T1IF R/W SPIF R/W TCIF R/W Bank 1 0X0E EIMR EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0 R/W R/W R/W R/W R/W R/W R/W R/W Bank 1 0X0F EISR EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0 R/W R/W T2IE R/W R/W T2EN R/W R/W R/W R/W T2P2 R/W R/W T2P1 R/W R/W T2P0 R/W T2IF R/W T2MS1 T2MS0 R/W R/W Bank 2 0X09 T2CR The EM78P510N has ten interrupt sources as listed below: TCC overflow interrupt External interrupt pin Watch timer interrupt Timer 1 overflow interrupt Timer 2 overflow interrupt A/D conversion complete interrupt UART transmit interrupt SPI transmit/receive interrupt Low voltage detector This IC has internal interrupts which are falling edge triggered, as follows: TCC timer overflow interrupt, and two 8-bit upper counter/timer overflow interrupt. If these interrupt sources change signal from high to low, the RF register will generate a "1" flag to the corresponding register if RE register is enabled. RF is the interrupt status register which records the interrupt request in flag bit. RE is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from address 0003H~001BH according to the interrupt source. For EM78P510N, each individual interrupt source has its own interrupt vector as depicted in Table 7. Before the interrupt subroutine is executed, the contents of ACC, R3[4:0], R5 and the R6 register will be saved by hardware. After the interrupt service routine is finished, ACC, R3[4:0], R5 and R6 will be pushed back. While in interrupt service routine, other interrupt service routine should not be allowed to be executed, so if other interrupts occur in an interrupt service routine, the hardware will save this interrupt, after which when interrupt service routine is completed, the next interrupt service routine will be executed. 58 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Interrupt sources ACC ENI/DISI R3[4:0] R5 R6 Interrupt occurs STACKACC STACKR3 RETI STACKR5 STACKR6 Fig. 6-15 Interrupt Backup Diagram Table 7 Interrupt Vector Interrupt Vector 0003H 0006H 0009H 000CH 000FH 0012H 0015H 0018H 001BH Interrupt Status TCC overflow interrupt External interrupt Watch timer interrupt Timer 1 overflow interrupt Timer 2 overflow interrupt A/D conversion complete interrupt UART transmit/receive complete interrupt SPI transmit/receive complete interrupt Low voltage detector interrupt 6.9 LCD Driver Registers for LCD Driver Circuit R_BANK Address Bank 1 0X05 Name LCDCR Bit 7 Bit 6 Bit 5 BS1 R/W Bit 4 BS0 R/W Bit 3 DS1 R/W Bit 2 DS0 R/W Bit 1 LCDF1 R/W Bit 0 LCDF0 R/W LCDEN LCDTYPE R/W R/W Bank 1 0X06 LCDAR 0 0 0 LCD_A4 R/W LCD_A3 R/W LCD_A2 LCD_A1 LCD_A0 R/W R/W R/W Bank 1 0X07 LCDBR LCD_D7 R/W LCD_D6 R/W LCD_D5 LCD_D4 R/W R/W LCD_D3 R/W LCD_D2 LCD_D1 LCD_D0 R/W R/W R/W Bank 1 0X08 LCDVCR 0 0 0 LCDC1 R/W LCDC0 R/W LCDVC2 LCDVC1 LCDVC0 R/W R/W R/W Bank 1 0X09 LCDCCR CON7 R/W CON6 R/W CON5 R/W CON4 R/W CON3 R/W CON2 R/W CON1 R/W CON0 R/W Bank 1 0X0A~0X0C LCDSCR0~2 SEG R/W SEG R/W SEG R/W SEG R/W SEG R/W SEG R/W SEG R/W SEG R/W Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 59 EM78P510N 8-Bit Microcontrollers The EM78P510N can drive LCD, up to 23 segments and 8 commons that can drive 8x23 dots totally. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins and LCD operating power supply pins. This circuit can work on normal mode, green mode and idle mode. The LCD duty, bias, the number of segment, the number of common and frame frequency are determined by the LCD controller register. The basic structure contains a timing control which use the main system clock or subsystem clock to generate the proper timing for different duty and display access. The R5 register is command register for LCD driver that include LCD enable/disable, bias (1/2, 1/3 and 1/4), duty (Static, 1/3, 1/4, 1/8) and LCD frame frequency control. The register bank 1 R6 is LCD RAM address control register. The register bank 1 R7 is LCD RAM data buffer. The register bank1 R8 is LCD contrast control and LCD clock register. The control register is explained below. 6.9.1 R5 LCDCR (LCD Control Register) Bit 7 LCDEN Bit 6 LCDTYPE Bit 5 BS1 Bit 4 BS0 Bit 3 DS1 Bit 2 DS0 Bit 1 LCDF1 Bit 0 LCDF0 Bit 7 (LCDEN): LCD Enable Select Bit 0 : disable LCD Circuit. All common/segment outputs are set to VDD Level. 1 : enable LCD circuit Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit 0 : A type wave 1 : B type wave Bits 5~4 (BS1~BS0): LCD Bias Select Bits BS1 0 0 1 BS0 0 1 X LCD Bias Select 1/2 Bias 1/3 Bias 1/4 Bias Bits 3~2 (DS1~DS0): LCD Duty Select Bits DS1 0 0 1 1 DS0 0 1 0 1 LCD Duty Static 1/3 Duty 1/4 Duty 1/8 Duty 60 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bits 1~0 (LCDF1~LCDF0): LCD Frame Frequency Control Bits LCD Frame Frequency (e.q. Fs =32.768K) LCDF1 LCDF0 0 0 1 1 0 1 0 1 Static 1/3 Duty 1/4 Duty Fs/(128*4) = 64 1/8 Duty Fs/(64*8) = 64.0 Fs/(512*1) = 64.0 Fs/(172*3) =63.5 Fs/(560*1) = 58.5 Fs/(188*3) = 58 Fs/(140*4) = 58.5 Fs/(70*8) = 58.5 Fs/(608*1) = 53.9 Fs/(204*3) = 53.5 Fs/(152*4) = 53.9 Fs/(76*8) = 53.9 Fs/(464*1) = 70.6 Fs/(156*3) = 70 Fs/(116*4) = 70.6 Fs/(58*8) = 70.6 6.9.2 R6 LCDADDR (LCD Address Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 LCD_A4 Bit 3 LCD_A3 Bit 2 LCD_A2 Bit 1 LCD_A1 Bit 0 LCD_A0 Bits 7~5: Reserved Bits 4~0 (LCD_A4~LCD_A0): LCD RAM Address R6 R7 (LCD data buffer) Segment (LCD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 address) (LCD_D7) (LCD_D6) (LCD_D5) (LCD_D4) (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0) 00H 01H 02H | 14H 15H 16H Common COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 | SEG20 SEG21 SEG22 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 61 EM78P510N 8-Bit Microcontrollers 6.9.3 R7 LCDBR (LCD Data Buffer) Bit 7 LCD_D 7 Bit 6 LCD_D 6 Bit 5 LCD_D 5 Bit 4 LCD_D 4 Bit 3 LCD_D 3 Bit 2 LCD_D 2 Bit 1 LCD_D 1 Bit 0 LCD_D 0 Bits 7~0 (LCD_D7~LCD_D0): LCD RAM Data Transfer Register * When the value of the display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off VDD R VLCD1 6R R MUX VLCD2 R VLCD3 0.6 R 0.8 R BS0 ~ BS1 VLCD R 0.8 R MUX 0.5 R 0.6R LCDVC0 ~ LCDVC2 0.3 R 0.4 R VSS 6.9.4 R8 LCDVCR (LCD Voltage Control Register) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 LCDC1 Bit 3 LCDC0 Bit 2 LCDVC2 Bit 1 LCDVC1 Bit 0 LCDVC0 Bits 7~5: Reserved Bits 4~3 (LCDC1~LCDC0): LCD Clock LCDC1 0 0 1 1 LCDC0 0 1 0 1 Fm 16M 8M 4M 2M FLCD Fc/29 Fc/28 Fc/27 Fc/26 When the main oscillator operates in crystal mode and there is no sub-oscillator, it is a must to set these two bits used for LCD clock. 62 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bit 2~0 (LCDVC2~LCDVC0): LCD Voltage Control Bits LCDVC2 0 0 0 0 1 1 1 1 LCDVC1 0 0 1 1 0 0 1 1 LCDVC0 0 1 0 1 0 1 0 1 Output 0.4VDD ~ VDD 0.34VDD ~ VDD 0.26VDD ~ VDD 0.18VDD ~ VDD 0.13VDD ~ VDD 0.07VDD ~ VDD 0.04VDD ~ VDD 0V ~ VDD Select LCD Clock Frame COM NonSelect VDD VLCD VDD SEG VLCD VDD COM-SEG VLCD -VDD Static Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 63 EM78P510N 8-Bit Microcontrollers 1frame VDD COM 0 VLCD3 VLCD VDD COM 1 VLCD3 VLCD VDD COM 2 VLCD3 VLCD VDD SEG N VLCD3 VLCD VDD VLCD3 SEG N - COM0 ON VLCD -VLCD3 -VDD VDD VLCD3 SEG N - COM1 OFF VLCD -VLCD3 -VDD 1/2 bias, 1/3 duty B type 1frame VDD COM 0 VLCD3 VLCD VDD COM 1 VLCD3 VLCD VDD COM 2 VLCD3 VLCD VDD SEG N VLCD3 VLCD VDD VLCD3 SEG N - COM0 ON VLCD -VLCD3 -VDD VDD VLCD3 SEG N - COM1 OFF VLCD -VLCD3 -VDD 1/2 bias, 1/4 duty B type 64 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 1frame VDD COM 0 VLCD3 VLCD VDD COM 1 VLCD3 VLCD VDD COM 2 VLCD3 VLCD VDD SEG N VLCD3 VLCD VDD VLCD3 SEG N - COM0 ON VLCD -VLCD3 -VDD VDD VLCD3 SEG N - COM1 OFF VLCD -VLCD3 -VDD 1/2 bias, 1/8 duty B type 1 frame VDD COM 0 VLCD2 VLCD3 VLCD VDD COM 1 VLCD2 VLCD3 VLCD VDD COM 2 VLCD2 VLCD3 VLCD SE GN VDD VLCD2 VLCD3 VLCD VDD SE G N - COM0 ON VLCD3 VLCD -VLCD3 -VDD VDD SE G N - COM1 OFF VLCD3 VLCD -VLCD3 -VDD 1/3 bias, 1/3 duty B type Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 65 EM78P510N 8-Bit Microcontrollers 1 frame VDD COM 0 VLCD2 VLCD3 VLCD VDD COM 1 VLCD2 VLCD3 VLCD VDD COM 2 VLCD2 VLCD3 VLCD SEG N VDD VLCD2 VLCD3 VLCD VDD SEG N - COM0 ON VLCD3 VLCD -VLCD3 -VDD VDD SEG N - COM1 OFF VLCD3 VLCD -VLCD3 -VDD 1/3 bias, 1/4 duty B type 1 frame VDD VLCD2 VLCD3 VLCD VDD VLCD2 VLCD3 VLCD VDD VLCD2 VLCD3 VLCD VDD VLCD2 VLCD3 VLCD VDD VLCD3 VLCD2 VLCD -VLCD2 -VLCD3 -VDD VDD VLCD3 VLCD2 VLCD -VLCD2 -VLCD3 -VDD COM 0 COM 1 COM 2 SEG N SEG N - COM0 ON SEG N - COM1 OFF 1/3 bias, 1/8 duty B type 66 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Select Frame V DD V LCD1 COM 0 V LCD2 V LCD3 V LCD V DD V LCD1 COM 1 VLCD2 VLCD3 V LCD VD D VLCD1 COM 2 VLCD2 VLCD3 V LCD VD D V LCD1 SEGN VLCD2 V LCD3 VLCD VD D VLCD1 VLCD2 VLCD3 SEGN-COM0 V LCD -VLCD3 -V LCD 2 -V LCD 1 -V DD VD D VLCD1 V LCD2 V LCD3 SEGN-COM1 VLCD -V LCD 3 -V LCD 2 -V LCD 1 -V DD 1/4 Bias 1/3 Duty Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 67 EM78P510N 8-Bit Microcontrollers Select Frame VDD VLCD1 COM 0 VLCD2 VLCD3 VLCD VDD VLCD1 COM 1 VLCD2 VLCD3 VLCD VDD VLCD1 COM 2 VLCD2 VLCD3 VLCD VDD VLCD1 SEGN VLCD2 VLCD3 VLCD VDD VLCD1 VLCD2 VLCD3 SEGN-COM0 VLCD -VLCD3 -VLCD2 -VLCD1 -VDD VDD VLCD1 VLCD2 VLCD3 SEGN-COM1 VLCD -VLCD3 -VLCD2 -VLCD1 -VDD 1/4 Bias 1/4 Duty 68 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Select Frame VDD VLCD1 COM 0 VLCD2 VLCD3 VLCD VDD VLCD1 COM 1 VLCD2 VLCD3 VLCD VDD VLCD1 COM 2 VLCD2 VLCD3 VLCD VDD VLCD1 SEGN VLCD2 VLCD3 VLCD VDD VLCD1 VLCD2 VLCD3 SEGN-COM0 VLCD -VLCD3 -VLCD2 -VLCD1 -VDD VDD VLCD1 VLCD2 VLCD3 SEGN-COM1 VLCD -VLCD3 -VLCD2 -VLCD1 -VDD 1/4 Bias 1/8 Duty Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 69 EM78P510N 8-Bit Microcontrollers 6.10 A/D Converter Registers for AD Converter Circuit R_BANK Address NAME Bank 3 0X09 Bit 7 ADRUN R/W Bit 6 ADP R/W Bit 5 Bit 4 Bit 3 Bit 2 ADIS2 R/W Bit 1 ADIS1 R/W Bit 0 ADIS0 R/W ADCR ADCK1 ADCK0 ADIS3 R/W R/W R/W Bank 3 0x0A ADICH CALI R/W ADREF R/W ADE11 ADE10 R/W R/W ADE9 R/W ADE8 R/W Bank 3 0X0B ADICL ADE7 R/W ADE6 R/W ADE5 R/W ADE4 R/W ADE3 R/W ADE2 R/W ADE1 R/W ADE0 R/W Bank 3 0X0C ADDH ADD11 ADD10 ADD9 R R R ADD8 R ADD7 R ADD6 R ADD5 R ADD4 R Bank 3 0X0D ADDL SIGN R/W VOF[2] VOF[1] VOF[0] R/W R/W R/W ADD3 R ADD2 R ADD1 R ADD0 R Bank 0 0x0E IMR T1IE R/W LVDIE ADIE R/W R/W SPIE R/W URTIE EXIE9 EXIE8 TCIE R/W R/W R/W R/W Bank 0 0x0F ISR T1IF R/W LVDIF ADIF R/W R/W SPIF R/W URTIF EXIF9 EXIF8 R/W R/W R/W TCIF R/W A D 1 1 (P B 7 ) A D 1 0 (P B 6 ) A D 9 (P B 5 ) 12 to 1 Analog switch A D 8 (P B 4 ) A D 7 (P A 3 ) A D 6 (P A 2 ) A D 5 (P A 1 ) A D 4 (P A 0 ) A D 3 (P 7 7 ) A D 2 (P 7 6 ) A D 1 (P 7 5 ) A D 0 (P 7 4 ) VDD VREF ADC (S u c c e s s iv e A p p ro x im a tio n ) Power Down S ta rt to C o n v e rt F o s c /4 F o s c /1 6 F o s c /3 2 F o s c /6 4 4 to 1 MUX A D IC L A D IC H 7-0 11 - 8 3 2 1 0 5 ADCR 4 IS R 5 5 IM R 11 10 9 8 7 6 5 4 3 2 1 0 ADCR 7 6 6 A D IC H ADCR DATA BUS Fig. 6-16 AD Converter This is a 12-bit successive approximation type AD converter. The upper side of analog reference voltage can select either internal VDD or external input pin P84 (VREF) by setting the ADREF bit in ADICH. 70 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.10.1 ADC Data Register When the A/D conversion is completed, the result is loaded to the ADDH (8-bit) and ADDL (4-bit). The START/END bit is cleared, and the ADIF is set. 6.10.2 A/D Sampling Time The accuracy, linearity, and speed of the successive approximation A/D converter are dependent on the properties of the ADC. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2 s for each K of the analog source impedance and at least 2 s for the low-impedance source. The maximum recommended impedance for the analog source is 10K at VDD =5V. After the analog input channel is selected, this acquisition time must be done before A/D conversion can be started. 6.10.3 A/D Conversion Time ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D conversion. For the EM78P510N, the conversion time per bit is about 4s. Table 8 shows the relationship between Tct and the maximum operating frequencies. Table 8 ADCK1:0 Operation Mode 00 01 10 11 Fc/4 Fc/16 Fc/32 Fc/64 Max. Frequency (Fc) 1MHz 4MHz 8MHz 16MHz Max. Conversion Rate per Bit 250kHz (4s) 250kHz (4s) 250kHz (4s) 250kHz (4s) Max. Conversion Rate 56us(17.86kHz) 56us(17.86kHz) 56us(17.86kHz) 56us(17.86kHz) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 71 EM78P510N 8-Bit Microcontrollers 6.11 UART (Universal Asynchronous Receiver/Transmitter) Registers for UART Circuit R_BANK Address NAME Bank 3 0X05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXE R/W URC URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE W R/W R/W R/W R/W R/W R Bank 3 0X06 URS URRD8 R EVEN R/W PRE R/W PRERR OVERR FMERR URBF R R R R RXE R/W Bank 3 0X07 URRD URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0 R R R R R R R R Bank 3 0X08 URTD URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0 W W W W W W W W Bank 5 0x06 UARC2 UARTE R/W UINVEN R/W Bank 0 0x0E IMR T1IE R/W LVDIE R/W ADIE R/W SPIE R/W URTIE EXIE9 EXIE8 TCIE R/W R/W R/W R/W Bank 0 0x0F ISR T1IF R/W LVDIF R/W ADIF R/W SPIF R/W URTIF EXIF9 EXIF8 R/W R/W R/W TCIF R/W Fig 6-17 Function Block Diagram In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible since the UART has independent transmit and receive sections. Double buffering for both sections allows the UART to be programmed for continuous data transfer. 72 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers The figure below shows the general format of one character sent or received. The communication channel is normally held in the marked state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit. If present, then the stop bit or bits (high) confirm the end of the frame. In receiving, the UART synchronizes on the falling edge of the start bit. When two or three "0" are detected during three samples, it is recognized as normal start bit and the receiving operation is started. START bit D0 D1 D2 Dn Parity STOP bit bit Idle state (mark) 1 bit 7 or 8 bits One character or frame 1 bit 1 bits Fig 6-18 Data Format in UART 6.11.1 UART Mode There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the addition of a parity bit. The parity bit addition is not available in Mode 3. Figure 6-19 below shows the data format in each mode. UMODE PRE 0 1 1 START 2 3 4 5 6 7 8 9 STOP 10 11 Mode 1 0 0 0 0 7 bits DATA 7 bits DATA START Parity STOP Mode 2 0 0 1 1 0 1 START 8 bits DATA 8 bits DATA STOP START Parity STOP Mode 3 1 0 X START 9 bits DATA STOP Fig 6-19 UART Model Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 73 EM78P510N 8-Bit Microcontrollers 6.11.2 Transmitting In transmitting serial data, the UART operates as follows: 1. Set the TXE bit of the URC register to enable the UART transmission function. 2. Write data into the URTD register and the UTBE bit of the URC register will be set by hardware. 3. Then start transmitting. 4. Serially transmitted data are transmitted in the following order from the TX pin. 5. Start bit: one "0" bit is output. 6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB. 7. Parity bit: one parity bit (odd or even selectable) is output. 8. Stop bit: one "1" bit (stop bit) is output. Mark state: output "1" continues until the start bit of the next transmitted data. After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled). 6.11.3 Receiving In receiving, the UART operates as follows: 1. Set RXE bit of the URS register to enable the UART receiving function. The UART monitors the RX pin and synchronizes internally when it detects a start bit. 2. Receive data is shifted into the URRD register in the order from LSB to MSB. 3. The parity bit and the stop bit are received. After one character is received, the URBF bit of the URS register will be set to 1. This means UART interrupt will occur. 4. The UART makes the following checks: (a) Parity check: The number of 1 of the received data must match the even or odd parity setting of the EVEN bit in the URS register. (b) Frame check: The start bit must be 0 and the stop bit must be 1. (c) Overrun check: The URBF bit of the URS register must be cleared (that means the URRD register should be read out) before the next received data is loaded into the URRD register. If any checks failed, the URTIF interrupt will be generated (if enabled), and an error flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be cleared by software otherwise, URTIF interrupt will occur when the next byte is received. 5. Read received data from URRD register. And URBF bit will be cleared by hardware. 74 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.11.4 Baud Rate Generator The baud rate generator is comprised of a circuit that generates a clock pulse to determine the transfer speed for transmission/reception in the UART. The BRATE2~BRATE0 bits of the URC register can determine the desired baud rate. 6.11.5 UART Timing 1. Transmission Counter Timing: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 TSYSTEM/16 One bit cycle TXD pin Start bit Bit 0 2. Receiving Counter Timing: Synchronization (Reset counter) 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 TSYSTEM/16 One bit cycle RXD pin Sampling Timing Stop bit Start bit Bit 0 3. UART Transmit operation (8 bits data with parity bit): TXD pin UTBE URTIF START bit D 0 D1 D2 Dn Parity STOP bit bit START bit D0 D1 D2 Clear by hardware when write data into UARTTx . And start transmitting. Clear by software Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 75 EM78P510N 8-Bit Microcontrollers 4. UART Receive operation (8 bits data with parity and stop bit): RXD pin START bit Synchronization D0 D1 D2 Dn Parity STOP START bit bit bit D0 D1 D2 Sample Timing URBF Clear by hardware when read data fromUARTRx Clear by software URTIF PRERR OVERR FMERR 6.12 SPI (Serial Peripheral Interface) 6.12.1 Overview & Features Overview: Figures 6-20 and 6-21 shows how the EM78P510N communicates with other devices through SPI module. If the EM78P510N is a master controller, it sends clock through the SCK pin. A couple of 8-bit data are transmitted and received at the same time. However, if the EM78P510N is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted based on both the clock rate and the selected edge. You can also set SPIS bit 7 (DORD) to determine the SPI transmission order, SPIC Bit 3 (SDOC) to control the SO pin after serial data output status and SPIS Bit 6 (TD1), Bit 5 (TD0) determines the SO status output delay times. Features: Operation in either Master mode or Slave mode Full duplex, three-wire synchronous communication Programmable baud rates of communication Programming clock polarity, (RD Bit 7) Interrupt flag available for the read buffer full SPI transmission order After serial data output SDO status select SDO status output delay times Up to 8 MHz (maximum) bit frequency 76 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers SO SPIR Reg SPIW SPIW Reg Reg /SS SPIS Reg Bit 7 Master Device SCK Slave Device SI SPI Module SPIR Reg SPIW SPIW Reg Reg Fig. 6-20 SPI Master/Slave Communication Fig. 6-21 SPI Configuration of Single-Master and Multi-Slave Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 77 EM78P510N 8-Bit Microcontrollers 6.12.2 SPI Function Description Read Write RBF Set to 1 RBFI SPIR reg SE SPIW reg Buffer Full Detector SPIS PA4/SEG4/SI bit 0 reg shift right bit 7 SPIC reg PA5/SEG5/SO Edge Select SBR0 ~SBR2 PA7/SEG7//SS / SS Prescaler 4, 8, 16, 32, 64 SBR2~SBR0 8 Clock Select 2 Noise Filter Tsco Edge Select TMR2 SPIC bit6 PA6/SEG6/SCK Fig. 6-22 SPI Block Diagram Fig. 6-23 The Function Block Diagram of SPI Transmission 78 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Below are the functions of each block and explanations on how to carry out the SPI communication with the signals depicted in Fig.6-22 and Fig.6-23. PA4/SEG4/SI: Serial Data In PA5/SEG5/SO: Serial Data Out PA6/SEG6/SCK:Serial Clock PA7/SEG7//SS: /Slave Select (Option). This pin (/SS) may be required during a slave mode RBF: Set by Buffer Full Detector, and reset by software Buffer Full Detector: Set to 1 when an 8-bit shifting is completed. SSE: Loads the data in SPIS register, and begin to shift SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS and the SPIW registers are loaded at the same time. Once data are written, SPIS starts transmission / reception. The data received will be moved to the SPIR register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the RBFI (Read Buffer Full Interrupt) flag are then set. SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must be read before the next reception is completed. The RBF flag is cleared as the SPIR register reads. SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit shifting is completed. The SSE bit will be kept in "1" if the communication is still undergoing. This flag must be cleared as the shifting is completed. Users can determine if the next write attempt is available. SBRS2~SBRS0: Programming the clock frequency/rates and sources. Clock Select:Selecting either the internal or the external clock as the shifting clock. Edge Select: Selecting the appropriate clock edges by programming the CES bit 6.12.3 SPI Signal & Pin Description The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows: PA4/SEG4/SI: Serial Data In, Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last, Defined as high-impedance, if not selected Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 79 EM78P510N 8-Bit Microcontrollers Program the same clock rate and clock edge to latch on both the master and slave devices The byte received will update the transmitted byte The RBF (located in Register 0x0C) will be set as the SPI operation is completed Timing is shown in Fig.6-23 and 6-24 PA5/SEG5/SO: Serial Data Out Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last Program the same clock rate and clock edge to latch on both the master and slave devices The received byte will update the transmitted byte The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed Timing is shown in Fig.6-23 and 6-24 PA6/SEG6/SCK: Serial Clock Generated by a master device Synchronize the data communication on both the SI and SO pins The CES (located in Register 0x0D) is used to select the edge to communicate. The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of communication The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode Timing is show in Fig.6-23 and 6-24 PA7/SEG7//SS: Slave Select; negative logic Generated by a master device to signify the slave(s) to receive data Goes low before the first cycle of SCK appears, and remains low until the last (eighth) cycle is completed Ignores the data on the SI and SO pins while /SS is high, because the SO is no longer driven Timing is shown in Fig.6-23 and 6-24 80 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Note: 1. The Priority of PA4/SEG4/SI Pin PA4/SEG4/SI Pin Priority High SI Medium SEG4 Low PA4 2. The Priority of PA5/SEG5/SO Pin PA5/SEG5/SO Pin Priority High SO Medium SEG5 Low PA5 3. The Priority of PA6/SEG6/SCK Pin PA6/SEG6/SCK Pin Priority High SCK Medium SEG6 Low PA6 4. The Priority of PA7/SEG7//SS PIN PA7/SEG7//SS Pin Priority High /SS Medium SEG7 Low PA7 6.12.4 Programming the Related Registers Registers for the SPI Circuit R_BANK Address Name Bank 2 0X0C Bit 7 DORD R/W Bit 6 TD1 R/W Bit 5 TD0 R/W Bit 4 - Bit 3 OD3 R/W Bit 2 OD4 R/W Bit 1 - Bit 0 RBF R SPIS Bank 2 0X0D SPIC CES R/W SPIE R/W SRO R/W SSE R/W SDOC SBRS2 SBRS1 SBRS0 R/W R/W R/W R/W Bank 2 0X0E SPIR SRB7 R/W SRB6 R/W SRB5 R/W SRB4 R/W SRB3 R/W SRB2 R/W SRB1 R/W SRB0 R/W Bank 2 0X0F SPIW SWB7 R/W SWB6 R/W LVDIE R/W LVDIF R/W SWB5 R/W ADIE R/W ADIF R/W SWB4 R/W SWB3 R/W URTIE R/W URTIF R/W SWB2 R/W EXIE9 R/W EXIF9 R/W SWB1 R/W EXIE8 R/W EXIF8 R/W SWB0 R/W TCIE R/W TCIF R/W BANK 0 0x0E IMR T1IE R/W SPIE R/W Bank 0 0x0F ISR T1IF R/W SPIIF R/W As the SPI mode is defined, the related registers of this operation are shown. Related Control Registers of the SPI Mode Address Bank 2 0x0D Bank 0 0x0E Name SPIC IMR Bit 7 CES Bit 6 SPIE Bit 5 SRO Bit 4 SSE SPIE Bit 3 SDOC Bit 2 SBR2 Bit 1 SBR1 Bit 0 SBR0 T1IE LVDIE ADIE URTIE EXIE9 EXIE8 TCIE SPIC: SPI Control Register * 81 Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bit 7 (CES): Clock Edge Select Bit 0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is on hold during a low-level. 1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is on hold during a high-level. Bit 6 (SPIE): SPI Enable Bit 0 : Disable SPI mode 1 : Enable SPI mode Bit 5 (SRO): SPI Read Overflow Bit 0 : No overflow 1 : A new data is received while the previous data is still being held in the SPIRB register. In the situation, the data in SPIS register will be destroyed. To avoid setting this bit, users are required to read the SPIRB register although only the transmission is implemented. This can only occur in slave mode. Bit 4 (SSE): SPI Shift Enable Bit 0 : Resets as soon as the shift is completed, and the next byte is read to shift. 1 : Starts to shift, and remained on "1" while the current byte is still being transmitted. Bit 3 (SDOC): SDO Output Status Control Bit 0 : After the serial data output, the SDO remain high. 1 : After the serial data output, the SDO remain low. Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits SBRS2 0 0 0 0 1 1 1 1 SBRS1 0 0 1 1 0 0 1 1 SBRS0 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Master Slave Slave SPI Baud Rate Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 Timer2 /SS enable /SS disable IMR: 82 * Interrupt Mask Register Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bit 4 (SPIE): Interrupt Enable Bit 0 : disable SPIF interrupt 1 : enable SPIF interrupt Related Status/Data Registers of the SPI Mode Address 0X0C 0x0E 0x0F Name SPIS SPIR SPIW Bit 7 DORD SRB7 SWB7 Bit 6 TD1 SRB6 SWB6 Bit 5 TD0 SRB5 SWB5 Bit 4 SRB4 SWB4 Bit 3 OD3 SRB3 SWB3 Bit 2 OD4 SRB2 SWB2 Bit 1 SRB1 SWB1 Bit 0 RBF SRB0 SWB0 SPIS: SPI Status Register Bit 7 (DORD): Data Shift Control Bit 0 : Shift left (MSB first) 1 : Shift right (LSB first). Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options TD1 0 0 1 1 TD0 0 1 0 1 Delay Time 8 CLK 16 CLK 24 CLK 32 CLK Bit 4: Reserved Bit 3 (OD3): Open-Drain Control Bit 1 : Open-drain enable for SDO 0 : Open-drain disable for SDO. Bit 2 (OD4): Open-Drain Control Bit 1 : Open-drain enable for SCK 0 : Open-drain disable for SCK. Bit 1: Reserved Bit 0 (RBF): Read Buffer Full Flag 1 : Receiving completed, and SPIRB is fully exchanged. 0 : Receiving not completed, and SPIRB has not fully exchanged. SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB from SPIS register. The RBF bit in the SPIS register will also be set. SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by and start to shift the data when sensing SCK edge with SSE set to "1". * 83 SPIWB: Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.12.5 SPI Mode Timing Fig. 6-24 SPI Mode with /SS Disabled The SCK edge is selected by programming bit CES. The waveform shown in Fig.6-24 is applicable regardless of whether the EM78P510N is in master or slave mode with /SS disabled. However, the waveform in Fig.6-25 can only be implemented in slave mode with /SS enabled. Fig. 6-25 SPI Mode with /SS Enabled 84 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.13 Timer/Counter 1 Registers for Timer/Counter 1 Circuit R_BANK Address Name Bank 2 0X05 Bit 7 TIS1 W Bit 6 TIS0 W Bit 5 T1MS2 W Bit 4 T1MS1 W Bit 3 T1MS0 W T2CCS R/W Bit 2 T1P2 W Bit 1 T1P1 W Bit 0 T1P0 W T1CR Bank 2 0X06 TSR T1MOD R/W TRCB R/W T1CSS1 T1CCS0 R/W R/W T1EN R/W T1OMS R/W T1OC R/W Bank 2 0X07 T1PD PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0] R/W R/W R/W R/W R/W R/W R/W R/W Bank 2 0X08 T1TD TD1[7] R/W TD1[6] R/W TD1[5] R/W TD1[4] R/W TD1[3] R/W TD1[2] R/W TD1[1] R/W TD1[0] R/W Bank 0 0x0E IMR T1IE R/W LVDIE R/W ADIE R/W SPIIE R/W URTIE R/W EXIE9 R/W EXIE8 R/W TCIE R/W Bank 0 0x0F ISR T1IF R/W LVDIF R/W ADIF R/W SPIF R/W URTIF R/W EXIF9 R/W EXIF8 R/W TCIF R/W Fig. 6-26 Timer/Counter 1 Configuration Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 85 EM78P510N 8-Bit Microcontrollers 6.13.1 Timer Mode In Timer mode, counting down is performed using the internal clock. The down-counter value auto reloads from T1PD. When the contents of the down-counter underflows, interrupt is generated and the counter is cleared. Counting down resumes after the counter is cleared. 6.13.2 T1OUT Mode In Timer 1 underflow Output mode, counting down is performed using the internal clock with prescaler or External clock through T1CLK Pin or Sub Frequency with prescaler. The counter value is loaded from T1PD, when the counter underflows. The F/F output is toggled and the counter is auto-reloaded from T1PD, each time an overflow is found. The F/F output is inverted and output to /T1OUT pin. This mode can generate 50% duty pulse output. The program can initialize the F/F and it is initialized to "0" during a reset. A T1OUT interrupt is generated each time the /T1OUT output is toggled. Fig 6-27 T1OUT Mode Timing Chart 6.13.3 Capture Mode In Capture mode, the pulse width, period and duty of the T1CAP input pin are measured in this mode, which can be used in decoding the remote control signal. The counter is free running by the internal clock. On the rising (falling) edge of T1CAP pin input, the contents of the counter is loaded into T1PD, then the counter is cleared and interrupt is generated. On the falling (rising) edge of T1CAP pin input, the contents of the counter are loaded into T1TD. The counter is still counting, on the next rising edge of the T1CAP pin input, the contents of the counter are loaded into T1PD, counter is cleared and interrupt is generated again. If an overflow occurs before the edge is detected, the 00H is loaded into T1PD and an underflow interrupt is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether the T1PD value is 00H. After an interrupt (capture to T1PD or overflow detection) is generated, capture and underflow detection are halted until T1PD is read out. 86 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Fig 6-28 Capture Mode Timing Chart 6.13.4 PWM Mode In Pulse Width Modulation (PWM) Output mode, counting down is performed using the internal clock with prescaler or external clock trough T1CLK Pin or Sub Frequency with prescaler. The Duty of PWM1 control by T1TD, and the period of PWM1 control by T1PD. The pulse at the PWM1 pin is held to high level as long as the counter value of T1TD greater than or equal to zero, while the pulse is held to low level until the counter value of T1PD is underflow. The F/F is toggled when underflow. The counter is still counting, the F/F is toggled again when the counter underflows, then the counter is auto reload from T1PD. The F/F output is inverted and output to the /PWM pin. A Timer1 interrupt is generated each time an underflow occurs. T1PD is configured as a 2-stage shift register and, during output, will not switch until one output cycle is completed even if T1PD is overwritten. Therefore, the output can be changed continuously. T1PD is also shifted the first time by setting T1S to "1" after data is loaded to T1PD. Fig 6-29 PWM Mode Timing Chart 6.13.5 16-Bit Mode In 16-bit timer mode, all function in Timer 1 resolution become 16 bits. Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 87 EM78P510N 8-Bit Microcontrollers 6.14 Timer 2 Registers for Timer/Counter 2 Circuit R_BANK Address NAME Bank 2 0X06 Bit 7 T1MOD R/W Bit 6 TRCB R/W Bit 5 Bit 4 Bit 3 T2CCS R/W Bit 2 T1EN R/W Bit 1 T1OMS R/W Bit 0 T1OC R/W TSR T1CSS1 T1CCS0 R/W R/W Bank 2 0X09 T2CR T2IF R/W T2IE R/W T2EN R/W T2MS1 R/W T2MS0 R/W T2P2 R/W T2P1 R/W T2P0 R/W Bank 2 0X0A T2PD PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] R/W R/W R/W R/W R/W R/W R/W R/W Bank 2 0X0B T2TD TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0] R/W R/W R/W R/W R/W R/W R/W R/W Fig 6-30 Timer 2 Configuration 88 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 6.14.1 Timer Mode In Timer mode, counting down is performed using the internal clock with prescaler. When the counter value from T2PD underflows, interrupt is then generated and the counter is cleared. Counting down resumes after the counter is cleared. The counter value will automatically reload from T2PD. Fig 6-31 Timer Mode Timing Chart 6.14.2 PWM Mode In Pulse Width Modulation (PWM) Output mode, counting down is performed using the internal clock with prescaler or Fsub with frequency. The PWM2 duty cycle is controlled by T2TD, and the PWM2 period is controlled by T2PD. The pulse at the PWM2 pin is held to high level as long as the T2TD counter value is greater than or equal to zero while the pulse is held to low level until the T2PD counter value underflows. Fig 6-32 PWM Mode Timing Chart Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 89 EM78P510N 8-Bit Microcontrollers 6.15 Code Options The EM78P510N has one Code Option word that is not part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 0 Bit 12~Bit 0 Word1 Bit 12~Bit 0 Word 2 Bit 12~Bit 0 1. Code Option Register (Word 0) Word 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TYPE1 TYPE0 LVREN LVRS1 LVRS0 ENWDTB FSMD FMMD1 FMMD0 HLP PR2 PR1 PR0 Bits 12~11 (TYPE1~TYPE0): Type Selection for 48 pins or 44 pins or 42 pins or 32 pins. TYPE1 0 0 1 1 TYPE0 0 1 0 1 Type Selection EM78P510 (32-pin SDIP/SOP) EM78P510 (42-pin DIP) EM78P510 (44-pin LQFP/QFP) EM78P510 (48-pin LQFP) (default) Bit 10 (LVREN): Low Voltage Reset Enable Bit 0 : Disable 1 : Enable Bits 9~8 (LVRS1~LVRS0): Low Voltage Reset Voltage Select Bits LVRS1 0 0 1 LVRS0 0 1 0 Reset Voltage 2.6V 3.3 V 3.9V Bit 7 (ENWDTB): Watchdog Timer Enable Bit 0 : Enable 1 : Disable Bits 6~4 (FSMD, FMMD1~FMMD0): Oscillator Modes Selection Bits FSMD 0 0 0 0 1 1 1 1 FMMD1 0 0 1 1 0 0 1 1 FMMD0 0 1 0 1 0 1 0 1 Main clock RC type (ERIC) Crystal type PLL type PLL type RC type (ERIC) Crystal type PLL type Crystal Sub-clock RC type (ERIC) RC type (ERIC) RC type (ERIC) RC type (ERIC) Crystal type Crystal type Crystal type None 90 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Bit 3 (HLP): Power Consumption Selection Bit 0 : Low power consumption, apply to working frequency at 4MHz or below 4MHz. 1 : High power consumption, apply to working frequency above 4MHz. Bits 2~0 (PR2~PR0): Protect Bit PR2~PR0 are protect bits, protect type are as follows: PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Protect Enable Enable Enable Enable Enable Enable Enable Disable 2. Code Option Register (Word 1) Word 1 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 -------HLFS --Bit 0 FCB0 FCB1 RESETB Bits 12~6 (Not used) Bit 5 (HLFS): Main or Sub Oscillator Select Bit 0 : CPU is selected as sub-oscillator when a reset occurs 1 : CPU is selected as main-oscillator when a reset occurs Bits 4~3 (Not used) Bits 2~1 (FCB1~FCB0): Frequency Select Bit FCB1 0 0 1 1 FCB0 0 1 0 1 Operation Frequency 100k~1M 1M~6M 6M~12M 12M~20M Bit 0 (RESETB): Reset Pin Enable Bit 0 : Enable, P81//RESET RESET pin 1 : Disable, P81//RESET P81 3. Customer ID Register (Word 2) Word 2 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Customer ID Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 91 EM78P510N 8-Bit Microcontrollers 6.16 Instruction Set Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one or more operand. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. The following are executed within two instruction cycles; "LJMP", "LCALL", or conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were tested to be true. Instructions written to the program counter are also executed within two instruction cycles. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on the I/O register. Convention: r = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0011 0 0000 0000 0100 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 Hex 0000 0001 0003 0004 0010 0011 0012 Mnemonic NOP DAA SLEP WDTC ENI DISI RET Operation No Operation Decimal Adjust A 0 WDT, Stop oscillator 0 WDT Enable Interrupt Disable Interrupt [Top of Stack] PC Status Affected None C T, P T, P None None None 92 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers Binary Instruction 0 0000 0001 0011 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr Hex 0013 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr Mnemonic RETI MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R Operation [Top of Stack] PC, Enable Interrupt AR 0A 0R R-A A R-A R R-1A R-1 R A R A ARR A&RA A & R R A R A ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero Status Affected None None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 93 EM78P510N 8-Bit Microcontrollers Binary Instruction 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1110 1010 kkkk k kkkk kkkk kkkk 1 01kk kkkk kkkk 1110 1011 kkkk k kkkk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0kkk kkkk 1 1111 kkkk kkkk 1 Hex 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1EAkkkk 1kkk 1EBkkkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E0K 1Fkk Mnemonic JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k LCALL k JMP k LJMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k BANK k ADD A,k Operation R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [Stack], (Page, k) PC PC+1 [Stack], K PC (Page, k) PC K PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A k R5(2:0) k+A A Status Affected None None None1 None None None None None None None Z Z Z None Z, C, DC None Z, C, DC Note: This instruction cannot operate under an interrupt flag. 94 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 7 Absolute Maximum Ratings Items Symbol VDD VI VO TOPR TSTG PD - Condition Min. - Port 7 ~ Port 9, Port A ~ Port C Port 7 ~ Port 9, Port A ~ Port C - - - - 2.3 GND-0.3 GND-0.3 -40 -65 - 32.768K Rating Max. 5.5 VDD+0.3 VDD+0.3 85 150 500 16M V V V C C mW Hz Unit Supply voltage Input voltage Output voltage Operation temperature Storage temperature Power dissipation Operating Frequency (2clk) 8 DC Electrical Characteristics 8.1 DC Electrical Characteristics Ta= 25 C, VDD= 5.0V5%, VSS= 0V Symbol Fc ERIC IIL VIH1 VIL1 VIHT1 VILT1 Parameter Crystal: VDD to 5V ERIC: VDD to 5V Input Leakage Current for input pins Input High Voltage (Schmitt Trigger) Input Low Voltage (Schmitt Trigger) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt Trigger) Condition Two cycle with two clocks R: 51K VIN = VDD, VSS Ports 7, 8, 9, A, B, C Ports 7, 8, 9, A, B, C /RESET, INT /RESET, INT OSCI in crystal mode OSCI in crystal mode VOH = VSS+2.1V VOH = VDD-0.5V VOL = VDD-2.1 VOL = VSS+0.5V Pull-high active, input pin at VSS Min. 0.1 F-20% -1 0.75VDD -0.3V 0.75VDD -0.3V 0.75VDD -0.3V 8 7 8 16 -70 Typ. Max. 16 Unit MHz MHz A V V V V V V mA mA mA mA A 2.2221 0 - - - - - - 10 9 10 18 -75 F+20% 1 VDD+0.3V 0.25VDD VDD+0.3V 0.25VDD VDD+0.3V 0.25VDD 15 12 15 21 -80 VIHX1 Clock Input High Voltage VILX1 Clock Input Low Voltage IOH1 IOH2 IOL1 IOL2 IPH1 Output High Voltage (Port 9) LED enabled Output High Voltage (Ports 7, 8, 9, A, B, C) Output Low Voltage (Port 9) LED enabled Output Low Voltage (Ports 7, 8, 9, A, B, C) Pull-high current Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 95 EM78P510N 8-Bit Microcontrollers Symbol ISB1 Parameter Stop mode Power down current Stop mode Power down current Condition WDT disabled Min. - Typ. 1.1 Max. - Unit A All input and I/O pins at VDD, Output pin floating ISB2 WDT enabled - 6.6 - A ICC1 Idle mode current /RESET= 'High', CPU OFF, Sub-oscillator clock (32.768kHz) ON, Output pin floating, WDT disabled /RESET= 'High', CPU OFF, Sub-oscillator clock (32.768kHz) ON, Output pin floating, WDT enabled, /RESET= 'High', CPU OFF, Sub-oscillator clock (32.768kHz) ON, Output pin floating, WDT disabled, LCD enabled /RESET= 'High', CPU ON, used Sub-oscillator clock (32.768kHz), Output pin floating, WDT enabled, /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled /RESET= 'High', Fosc=16MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled Ta = 25 C VLCD=5V, exclude CPU core operation current (not panel) VLCD=3V, exclude CPU core operation current (not panel) - 4.7 - A ICC2 Idle mode current - 10.3 - A ICC3 Idle mode current - 23.7 - A ICC4 Green mode current - 21.4 - A ICC5 Normal mode - 1.48 - mA ICC6 Normal mode LCD Voltage Dividing Resistor All LCD lighting All LCD lighting - 3.45 - mA RLCD ILCD1 ILCD2 - - - 80 23.3 12.9 - - - K A A * Typical values are based on characterization results at 25 C 96 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 8.2 A/D Converter Characteristic Vdd=2.5V to 5.5V,Vss=0V,Ta=-40 to 85 C Symbol VAREF VASS VAI IAI1 Ivdd Ivref Ivdd Ivref Parameter Condition Min 2.5 Vss VASS 750 -10 500 200 11 0 0 0 0 0 0 0 4.7 4 14 0 Typ - - - 850 0 600 250 12 4 0.5 4 2 8 - 0.2 4.8 - - - Max Vdd Vss VAREF 1000 +10 820 300 - 8 0.8 8 4 10 VAREF 0.3 5 - 14 2 Unit V V V A A A A Bits LSB LSB LSB LSB K V V s TAD LSB Analog reference voltage VAREF - VASS2.5V Analog input voltage Analog supply current - Vdd=VAREF=5.0V, VASS = 0.0V (V reference from Vdd) Vdd=VAREF=5.0V, VASS = 0.0V (V reference from VREF) Vdd=VAREF=5.0V, VASS = 0.0V Vdd = 2.5 to 5.5V Ta=25 Vdd = 2.5 to 5.5V Ta=25 Vdd=VAREF=5.0V, VASS = 0.0V Vdd=VAREF=5.0V, VASS = 0.0V - VDD =VAREF=5.0V, VASS = 0.0V VDD =VAREF=5.0V, VASS = 0.0V, RL=10K Vdd=VAREF=5.0V, VASS = 0.0V Vdd=VAREF=5.0V, VASS = 0.0V Vdd=5.0V0.5V IAI2 RN LN DNL FSE OE ZAI ADIV Analog supply current Resolution Linearity error Differential non-linear error Full scale error Offset error Recommended impedance of analog voltage source A/D input voltage range A/D output voltage swing A/D clock period A/D conversion time Power Supply Rejection ADOV TAD TCN PSR Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 97 EM78P510N 8-Bit Microcontrollers 8.3 Phase Lock Loop Characteristic 8.3.1 PLL DC Electrical Characteristic Symbol VD Parameter Digital Supply Voltage Condition - Min 2.3 Typ - Max 5.5 Unit V 8.3.2 AC Electrical Characteristic Parameter Input Clock CLK2 0 0 Output Clock 0 0 1 1 1 Current Consumption Lock Up Time Frequency Accuracy Condition - CLK1 0 0 1 1 0 0 1 Normal Power Down Mode - - CLK0 0 1 0 1 0 1 X Min - - - - - - - - - - - - -30 Typ 32.768 - 3.997 1.998 0.999 499.7 7.995 11.99 15.99 - - - - Max - - - - - - - - - 500 1 200 +30 Unit kHz - MHz MHz MHz KHz MHz MHz MHz A A s ppm 98 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers 9 AC Electrical Characteristics (Ta=- 40 C ~ 85 C, VDD=5V5%, GND=0V) Symbol Dclk Tins Tdrh Trst Twdt Tset Thold Tdelay Tiod Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time I/O delay for EMI enable Conditions - Crystal type RC type Ta = 25 C Ta = 25 C Ta = 25 C - - Cload=20pF Cload=150pF Min 45 100 500 11.3 2000 11.3 - - - 4 Typ 50 - - 16.2 - 16.2 0 20 50 5 Max 55 DC DC 21.6 - 21.6 - - - 6 Unit % ns ns ms ns ms ns ns ns ns Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 99 EM78P510N 8-Bit Microcontrollers 10 Timing Diagrams AC Test Input/Output Waveform VDD-0.5 0.7VDD 0.7VDD TEST POINTS 0.3VDD 0.3VDD VSS+0.5 AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc * n = 0, 2, 4, 6 100 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers APPENDIX A Package Type OTP MCU EM78P510NQ EM78P510NAQ EM78P510NBQ EM78P510NP EM78P510NK/AK EM78P510NM/AM Package Type LQFP LQFP QFP DIP SDIP SOP Pin Count 48 44 44 42 32 32 Package Size 7 mm x 7 mm 10 mm x 10 mm 10 mm x 10 mm 600 mil 400 mil 450 mil B Package Information B.1 48-Lead Low Profile Quad Flat Package (LQFP) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 101 EM78P510N 8-Bit Microcontrollers B.2 44-Lead Low Profile Quad Flat Package (LQFP) 102 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers B.3 44-Lead Quad Flat Package (QFP) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 103 EM78P510N 8-Bit Microcontrollers B.4 42-Lead Dual Inline Package (DIP) 104 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers B.5 32-Lead Shrink Dual Inline Package (SDIP) Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 105 EM78P510N 8-Bit Microcontrollers B.6 32-Lead Small Outline Package (SOP) 106 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers C EM78P510N Program Pin List DWTR is used to program the EM78P510N IC's. The connector of DWTR is selected by CON3 (EM78P447). The software is selected by EM78P510. Program Pin Name Pin #31 Pin #30 Pin #28 Pin #8 Pin #10 Pin #34 Pin #29 Pin #32 IC Pin Name P75 P76 P77 VDD VSS TEST PC2 PC3 LQFP-48 Pin Number 2 3 4 5 6 9 10 11 L/QFP-44 Pin Number 2 3 4 5 6 9 10 11 DIP-42 Pin Number 8 9 10 11 12 15 16 17 SDIP/SOP-32 Pin Number 29 30 31 32 1 4 5 6 D ICE 510 Oscillator circuit (JP4) D.1 Mode 1 Main oscillator: Crystal mode, Sub oscillator: Crystal mode Crystal GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND Crystal Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 107 EM78P510N 8-Bit Microcontrollers D.2 Mode2 Main oscillator: PLL mode, Sub oscillator: Crystal mode Crystal GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND PLL D.3 Mode3 Main oscillator: ERIC mode, Sub oscillator: Crystal mode Crystal GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND ERIC D.4 Mode4 Main oscillator: Crystal mode, Sub oscillator: ERIC mode ERIC GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND Crystal 108 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) EM78P510N 8-Bit Microcontrollers D.5 Mode5 Main oscillator: PLL mode, Sub oscillator: RC mode ERIC GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND PLL D.6 Mode6 Main oscillator: RC mode, Sub oscillator: RC mode ERIC GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND ERIC D.7 Mode7 Main oscillator: Crystal mode, Sub oscillator: None None GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI Sub oscillator Main oscillator JP4 GND Crystal Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) * 109 EM78P510N 8-Bit Microcontrollers E ICE 510 Output Pin Assignment (JP 3) 110 * Product Specification (V0.9) 09.12.2006 (This specification is subject to change without further notice) |
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